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Title: Structures for nitride vertical transistors

Abstract

A vertical semiconductor transistor and a method of forming the same. A vertical semiconductor transistor has at least one semiconductor region, a source, and at least one gate region. The at least one semiconductor region includes a III-nitride semiconductor material. The source is formed over the at least one semiconductor region. The at least one gate region is formed around at least a portion of the at least one semiconductor region.

Inventors:
;
Issue Date:
Research Org.:
Massachusetts Institute of Technology, Cambridge, MA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1568188
Patent Number(s):
10,256,352
Application Number:
15/388,963
Assignee:
Massachusetts Institute of Technology (Cambridge, MA)
DOE Contract Number:  
AR0000452
Resource Type:
Patent
Resource Relation:
Patent File Date: 12/22/2016
Country of Publication:
United States
Language:
English

Citation Formats

Sun, Min, and Palacios, Tomas Apostol. Structures for nitride vertical transistors. United States: N. p., 2019. Web.
Sun, Min, & Palacios, Tomas Apostol. Structures for nitride vertical transistors. United States.
Sun, Min, and Palacios, Tomas Apostol. Tue . "Structures for nitride vertical transistors". United States. https://www.osti.gov/servlets/purl/1568188.
@article{osti_1568188,
title = {Structures for nitride vertical transistors},
author = {Sun, Min and Palacios, Tomas Apostol},
abstractNote = {A vertical semiconductor transistor and a method of forming the same. A vertical semiconductor transistor has at least one semiconductor region, a source, and at least one gate region. The at least one semiconductor region includes a III-nitride semiconductor material. The source is formed over the at least one semiconductor region. The at least one gate region is formed around at least a portion of the at least one semiconductor region.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {4}
}

Patent:

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