Durable bond pad structure for electrical connection to extreme environment microelectronic integrated circuits

Spry, David J.; Lukco, Dorothy; Neudeck, Philip G.; Chang, Carl W.; Chen, Liangyu; Meredith, Roger D.; Moses, Kelley M.; Blaha, Charles A.; Gonzalez, Jose M.; Beheim, Glenn M.; Laster, Kimala L.

Title: Durable bond pad structure for electrical connection to extreme environment microelectronic integrated circuits

Abstract

A durable bond pad structure is described that facilitates highly durable electrical connections to semiconductor microelectronics chips (e.g., silicon carbide (SiC) chips) to enable prolonged operation over very extreme temperature ranges.

Inventors:: Spry, David J.; Lukco, Dorothy; Neudeck, Philip G.; Chang, Carl W.; Chen, Liangyu; Meredith, Roger D.; Moses, Kelley M.; Blaha, Charles A.; Gonzalez, Jose M.; Beheim, Glenn M.; Laster, Kimala L.

Issue Date:: 2019-04-09

Research Org.:: National Aeronautics and Space Administration (NASA), Washington, DC (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1568187

Patent Number(s):: 10256202

Application Number:: 15/880,139

Assignee:: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration (Washington, DC)

Patent Classifications (CPCs):: H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

Show more

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H01L2224/05015 - being circular or elliptic
H01L2224/02351 - comprising interlocking features
H01L2224/05193 - with a principal constituent of the material being a solid not provided for in groups H01L2224/051 - H01L2224/05191, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
H01L2224/05084 - Four-layer arrangements
H01L2224/05022 - the internal layer being at least partially embedded in the surface
H01L2924/3512 - Cracking
H01L2924/10272 - Silicon Carbide [SiC]
H01L2224/05009 - Bonding area integrally formed with a via connection of the semiconductor or solid-state body
H01L2224/05178 - Iridium [Ir] as principal constituent
H01L2924/04642 - SiC
H01L2224/05187 - Ceramics, e.g. crystalline carbides, nitrides or oxides
H01L2224/05181 - Tantalum [Ta] as principal constituent
H01L2224/05169 - Platinum [Pt] as principal constituent
H01L2224/02381 - Side view
H01L23/5226 - {Via connections in a multilevel interconnection structure}
H01L2224/04042 - Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
H01L2224/0235 - Shape of the redistribution layers
H01L24/05 - {of an individual bonding area}
H01L2224/45144 - Gold
H01L2224/0401 - Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
H01L2224/02233 - not in direct contact with the bonding area
H01L2924/00014 - the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
H01L2224/48463 - the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
H01L23/53257 - {the principal metal being a refractory metal}
H01L2924/013 - Alloys
H01L2924/0475 - 5th Group
H01L2224/05644 - Gold [Au] as principal constituent
H01L2224/05567 - the external layer being at least partially embedded in the surface

Show less

Resource Type:: Patent

Resource Relation:: Patent File Date: 01/25/2018

Country of Publication:: United States

Language:: English

Subject:: 42 ENGINEERING

Citation Formats


                    Spry, David J., Lukco, Dorothy, Neudeck, Philip G., Chang, Carl W., Chen, Liangyu, Meredith, Roger D., Moses, Kelley M., Blaha, Charles A., Gonzalez, Jose M., Beheim, Glenn M., and Laster, Kimala L. Durable bond pad structure for electrical connection to extreme environment microelectronic integrated circuits.  United States: N. p., 2019. 
        Web.

Copy to clipboard


                    Spry, David J., Lukco, Dorothy, Neudeck, Philip G., Chang, Carl W., Chen, Liangyu, Meredith, Roger D., Moses, Kelley M., Blaha, Charles A., Gonzalez, Jose M., Beheim, Glenn M., & Laster, Kimala L. Durable bond pad structure for electrical connection to extreme environment microelectronic integrated circuits.  United States.

Copy to clipboard


                    Spry, David J., Lukco, Dorothy, Neudeck, Philip G., Chang, Carl W., Chen, Liangyu, Meredith, Roger D., Moses, Kelley M., Blaha, Charles A., Gonzalez, Jose M., Beheim, Glenn M., and Laster, Kimala L. Tue .  
        "Durable bond pad structure for electrical connection to extreme environment microelectronic integrated circuits".  United States.  https://www.osti.gov/servlets/purl/1568187.

Copy to clipboard


                    
@article{osti_1568187,

  title        = {Durable bond pad structure for electrical connection to extreme environment microelectronic integrated circuits},

  author       = {Spry, David J. and Lukco, Dorothy and Neudeck, Philip G. and Chang, Carl W. and Chen, Liangyu and Meredith, Roger D. and Moses, Kelley M. and Blaha, Charles A. and Gonzalez, Jose M. and Beheim, Glenn M. and Laster, Kimala L.},

  abstractNote = {A durable bond pad structure is described that facilitates highly durable electrical connections to semiconductor microelectronics chips (e.g., silicon carbide (SiC) chips) to enable prolonged operation over very extreme temperature ranges.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {4}

}

Copy to clipboard

Patent:

View Patent

Save / Share:

Export Metadata

Save to My Library

Works referenced in this record:

Adhesion and/or encapsulation of silicon carbide-based semiconductor devices on ceramic substrates
patent, November 2001

Parsons, James D.; Kwak, B. Leo
US Patent Document 6,319,757
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6319757

Method for providing semiconductors having self-aligned ion implant
patent, May 2011

Neudeck, Philip G.
US Patent Document 7,935,601
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7935601

Method of making contacts on an integrated circuit
patent, August 1999

White, Lawrence K.
US Patent Document 5,942,448
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5942448

Electronic component package and method for forming same
patent, September 2016

Tran, Tu-Anh N.; Lee, Chu-Chung
US Patent Document 9,437,574
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9437574

Bonding pad and method for manufacturing it
patent, July 2002

Hsia, Chin-Chiu; Tsui, Bing-Yue; Yang, Tsung-Ju
US Patent Document 6,426,555
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6426555

Protection for bonding pads and methods of formation
patent, January 2011

Yu, I., Chen-Hua; Chiou, Wen-Chih; Wu, Weng-Jin
US Patent Document 7,872,357
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7872357

Bond pad structure to reduce bond pad corrosion
patent, March 2015

Chen, Ying-Ju; Chen, Hsien-Wei; Yu, Tsung-Yuan
US Patent Document 8,994,181
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8994181

Semiconductor component having a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer
patent, August 2015

Chen, Ying-Ju; Chen, Hsien-Wei
US Patent Document 9,105,588
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9105588

High temperature circuit structures with thin film layer
patent, January 2006

Parsons, James D.
US Patent Document 6,989,574
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6989574

Semiconductor device with bonding pad support structure
patent, July 2008

Oda, Noriaki
US Patent Document 7,397,125
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7397125

Bond pad structure with dual passivation layers
patent, June 2017

Wang, Ye
US Patent Document 9,691,703
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9691703

Iridium interfacial stack (IRIS)
patent, April 2015

Spry, David J.
US Patent Document 9,013,002
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9013002

Structure and method of forming a pad structure having enhanced reliability
patent, May 2014

Chen, Hsien-Wei; Chen, Ying-Ju
US Patent Document 8,723,325
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8723325

MEMS direct chip attach packaging methodologies and apparatuses for harsh environments
patent, January 2005

Okojie, Robert S.
US Patent Document 6,845,664
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6845664

Bond pad structure and method of manufacturing the same
patent, February 2016

Wang, Ye
US Patent Document 9,269,678
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9269678

Similar Records in DOE Patents and OSTI.GOV collections:

High density printed electrical circuit board card connection system

Patent Baumbaugh, Alan E [Aurora, IL]

A zero insertion/extraction force printed circuit board card connection system comprises a cam-operated locking mechanism disposed along an edge portion of the printed circuit board. The extrusions along the circuit board mate with an extrusion fixed to the card cage having a plurality of electrical connectors. The card connection system allows the connectors to be held away from the circuit board during insertion/extraction and provides a constant mating force once the circuit board is positioned. The card connection system provides a simple solution to the need for a greater number of electrical signal connections.
Full Text Available
L-connect routing of die surface pads to the die edge for stacking in a 3D array

Patent Petersen, Robert W [Dublin, CA]

Integrated circuit chips and method of routing the interface pads from the face of the chip or die to one or more sidewall surfaces of the die. The interconnection is routed from the face of the die to one or more edges of the die, then routed over the edge of the die and onto the side surface. A new pad is then formed on the sidewall surface, which allows multiple die or chips to be stacked in a three-dimensional array, while enabling follow-on signal routing from the sidewall pads. The routing of the interconnects and formation of the sidewallmore » « less
Full Text Available
Direct write with microelectronic circuit fabrication

Patent Drummond, Timothy [Ann Arbor, MI]; Ginley, David [Albuquerque, NM]

In a process for deposition of material onto a substrate, for example, the deposition of metals or dielectrics onto a semiconductor laser, the material is deposited by providing a colloidal suspension of the material and directly writing the suspension onto the substrate surface by ink jet printing techniques. This procedure minimizes the handling requirements of the substrate during the deposition process and also minimizes the exchange of energy between the material to be deposited and the substrate at the interface. The deposited material is then resolved into a desired pattern, preferably by subjecting the deposit to a laser annealing step.more » « less
Full Text Available
MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

Patent Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; ...

In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.
Full Text Available
Rolled-up transformer structure for a radiofrequency integrated circuit (RFIC)

Patent Li, Xiuling; Huang, Wen

A rolled-up transformer structure comprises a multilayer sheet having a rolled configuration comprising multiple turns about a longitudinal axis. The multilayer sheet comprises more than one conductive pattern layer on a strain-relieved layer, including a first conductive film and a second conductive film separated from the first conductive film in a thickness direction. The first conductive film comprises an even number of primary conductive strips, where each primary conductive strip has a length extending in the rolling direction, and the second conductive film comprises an even number of secondary conductive strips, where each secondary conductive strip has a length extendingmore » « less
Full Text Available

Similar Records

Title: Durable bond pad structure for electrical connection to extreme environment microelectronic integrated circuits

Abstract

Citation Formats

Adhesion and/or encapsulation of silicon carbide-based semiconductor devices on ceramic substrates patent, November 2001

Method for providing semiconductors having self-aligned ion implant patent, May 2011

Method of making contacts on an integrated circuit patent, August 1999

Electronic component package and method for forming same patent, September 2016

Bonding pad and method for manufacturing it patent, July 2002

Protection for bonding pads and methods of formation patent, January 2011

Bond pad structure to reduce bond pad corrosion patent, March 2015

Semiconductor component having a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer patent, August 2015

High temperature circuit structures with thin film layer patent, January 2006

Semiconductor device with bonding pad support structure patent, July 2008

Bond pad structure with dual passivation layers patent, June 2017

Iridium interfacial stack (IRIS) patent, April 2015

Structure and method of forming a pad structure having enhanced reliability patent, May 2014

MEMS direct chip attach packaging methodologies and apparatuses for harsh environments patent, January 2005

Bond pad structure and method of manufacturing the same patent, February 2016

Adhesion and/or encapsulation of silicon carbide-based semiconductor devices on ceramic substrates
patent, November 2001

Method for providing semiconductors having self-aligned ion implant
patent, May 2011

Method of making contacts on an integrated circuit
patent, August 1999

Electronic component package and method for forming same
patent, September 2016

Bonding pad and method for manufacturing it
patent, July 2002

Protection for bonding pads and methods of formation
patent, January 2011

Bond pad structure to reduce bond pad corrosion
patent, March 2015

Semiconductor component having a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer
patent, August 2015

High temperature circuit structures with thin film layer
patent, January 2006

Semiconductor device with bonding pad support structure
patent, July 2008

Bond pad structure with dual passivation layers
patent, June 2017

Iridium interfacial stack (IRIS)
patent, April 2015

Structure and method of forming a pad structure having enhanced reliability
patent, May 2014

MEMS direct chip attach packaging methodologies and apparatuses for harsh environments
patent, January 2005

Bond pad structure and method of manufacturing the same
patent, February 2016