Error detection and correction utilizing locally stored parity information

Nair, Prashant Jayaprakash; Roberts, David A.

Title: Error detection and correction utilizing locally stored parity information

Abstract

A processing system includes a memory coupled to a processor. The memory stores data blocks, with each data block having a separate associated checksum value stored along with the data block in the memory. The processor has a storage location that stores parity information for the data blocks, with the parity information having a plurality of parity blocks. Each parity block represents a parity of a corresponding set of data blocks. The parity blocks can be accessed for use in error detection and correction schemes used by the processing system.

Inventors:: Nair, Prashant Jayaprakash; Roberts, David A.

Issue Date:: 2019-04-02

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1568154

Patent Number(s):: 10248497

Application Number:: 14/521,183

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/1004 - {to protect a block of data words, e.g. CRC or checksum
G06F11/108 - {Parity data distribution in semiconductor storages, e.g. in SSD}

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DOE Contract Number:: AC52-07NA27344; B600716

Resource Type:: Patent

Resource Relation:: Patent File Date: 10/22/2014

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Nair, Prashant Jayaprakash, and Roberts, David A. Error detection and correction utilizing locally stored parity information.  United States: N. p., 2019. 
        Web.

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                    Nair, Prashant Jayaprakash, & Roberts, David A. Error detection and correction utilizing locally stored parity information.  United States.

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                    Nair, Prashant Jayaprakash, and Roberts, David A. Tue .  
        "Error detection and correction utilizing locally stored parity information".  United States.  https://www.osti.gov/servlets/purl/1568154.

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@article{osti_1568154,

  title        = {Error detection and correction utilizing locally stored parity information},

  author       = {Nair, Prashant Jayaprakash and Roberts, David A.},

  abstractNote = {A processing system includes a memory coupled to a processor. The memory stores data blocks, with each data block having a separate associated checksum value stored along with the data block in the memory. The processor has a storage location that stores parity information for the data blocks, with the parity information having a plurality of parity blocks. Each parity block represents a parity of a corresponding set of data blocks. The parity blocks can be accessed for use in error detection and correction schemes used by the processing system.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {4}

}

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Works referenced in this record:

Error detection and correction code for data and check code fields
patent, March 2000

Yamauchi, Alan M.
US Patent Document 6,041,430
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6041430

Methods and apparatus for correcting data and error detection codes on the fly
patent, March 2007

James, Michael; Ono, Kana
US Patent Document 7,191,382
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7191382

Circuit for and method of implementing a plurality of circuits on a programmable logic device
patent, August 2008

Drimer, Saar; Moore, Jason J.; Lesea, Austin H.
US Patent Document 7,408,381
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7408381

Memory-based error recovery
patent, January 2013

Yu, Shu-Yi; Keil, Shane; Edmondson, John H.
US Patent Document 8,365,015
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8365015

Protection of data in memory
patent, February 2016

Ellis, Jackson; Cohen, Earl T.; Sambandan, Sivakumar
US Patent Document 9,250,995
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9250995

Shared cache for data integrity operations
patent, February 2004

Morrison, John
US Patent Document 6,687,791
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6687791

Method and apparatus for recovering from correctable ECC errors
patent, June 1999

Wu, Chang-Hong; Lauterbach, Gary R.
US Patent Document 5,912,906
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5912906

System and method of reading non-volatile computer memory
patent, August 2008

Baker, David Cureton; Abbott, Grayson Dale; Zeevi, Josef
US Patent Document 7,409,623
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7409623

Error correcting device, method of error correction thereof, and memory device and data processing system including of the same
patent, November 2012

Chang, Sil Wan; Yu, Bum-Seok; Jeong, Sangoh Kyoo
US Patent Document 8,316,280
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8316280

Method of correcting errors stored in a memory array
patent, May 2009

Lesea, Austin H.
US Patent Document 7,539,926
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7539926

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Title: Error detection and correction utilizing locally stored parity information

Abstract

Citation Formats

Error detection and correction code for data and check code fields patent, March 2000

Methods and apparatus for correcting data and error detection codes on the fly patent, March 2007

Circuit for and method of implementing a plurality of circuits on a programmable logic device patent, August 2008

Memory-based error recovery patent, January 2013

Protection of data in memory patent, February 2016

Shared cache for data integrity operations patent, February 2004

Method and apparatus for recovering from correctable ECC errors patent, June 1999

System and method of reading non-volatile computer memory patent, August 2008

Error correcting device, method of error correction thereof, and memory device and data processing system including of the same patent, November 2012

Method of correcting errors stored in a memory array patent, May 2009

Error detection and correction code for data and check code fields
patent, March 2000

Methods and apparatus for correcting data and error detection codes on the fly
patent, March 2007

Circuit for and method of implementing a plurality of circuits on a programmable logic device
patent, August 2008

Memory-based error recovery
patent, January 2013

Protection of data in memory
patent, February 2016

Shared cache for data integrity operations
patent, February 2004

Method and apparatus for recovering from correctable ECC errors
patent, June 1999

System and method of reading non-volatile computer memory
patent, August 2008

Error correcting device, method of error correction thereof, and memory device and data processing system including of the same
patent, November 2012

Method of correcting errors stored in a memory array
patent, May 2009