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Title: Error detection and correction utilizing locally stored parity information

Abstract

A processing system includes a memory coupled to a processor. The memory stores data blocks, with each data block having a separate associated checksum value stored along with the data block in the memory. The processor has a storage location that stores parity information for the data blocks, with the parity information having a plurality of parity blocks. Each parity block represents a parity of a corresponding set of data blocks. The parity blocks can be accessed for use in error detection and correction schemes used by the processing system.

Inventors:
;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1568154
Patent Number(s):
10248497
Application Number:
14/521,183
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344; B600716
Resource Type:
Patent
Resource Relation:
Patent File Date: 10/22/2014
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Nair, Prashant Jayaprakash, and Roberts, David A. Error detection and correction utilizing locally stored parity information. United States: N. p., 2019. Web.
Nair, Prashant Jayaprakash, & Roberts, David A. Error detection and correction utilizing locally stored parity information. United States.
Nair, Prashant Jayaprakash, and Roberts, David A. Tue . "Error detection and correction utilizing locally stored parity information". United States. https://www.osti.gov/servlets/purl/1568154.
@article{osti_1568154,
title = {Error detection and correction utilizing locally stored parity information},
author = {Nair, Prashant Jayaprakash and Roberts, David A.},
abstractNote = {A processing system includes a memory coupled to a processor. The memory stores data blocks, with each data block having a separate associated checksum value stored along with the data block in the memory. The processor has a storage location that stores parity information for the data blocks, with the parity information having a plurality of parity blocks. Each parity block represents a parity of a corresponding set of data blocks. The parity blocks can be accessed for use in error detection and correction schemes used by the processing system.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {4}
}

Works referenced in this record:

Circuit for and method of implementing a plurality of circuits on a programmable logic device
patent, August 2008


Memory-based error recovery
patent, January 2013


Protection of data in memory
patent, February 2016


Shared cache for data integrity operations
patent, February 2004


Method and apparatus for recovering from correctable ECC errors
patent, June 1999


System and method of reading non-volatile computer memory
patent, August 2008