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Title: Methods and systems of synchronizer selection

Abstract

A circuit includes a plurality of synchronizers to adapt a signal from a first clock domain to a second clock domain. Each synchronizer of the plurality of synchronizers includes a synchronizer input to receive the signal from the first clock domain and a synchronizer output to provide the signal as adapted to the second clock domain. The circuit also includes a multiplexer (mux) that includes a plurality of mux inputs and a mux output. Each mux input is coupled to the synchronizer output of a respective synchronizer of the plurality of synchronizers. The mux output provides the signal, as adapted to the second clock domain, from the synchronizer output of a selected synchronizer of the plurality of synchronizers.

Inventors:
; ;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1532154
Patent Number(s):
9,294,263
Application Number:
14/146,654
Assignee:
Advanced Micro Devices, Inc. (Sunnyvale, CA)
DOE Contract Number:  
AC52-07NA27344; B600716
Resource Type:
Patent
Resource Relation:
Patent File Date: 2014-01-02
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING; 97 MATHEMATICS AND COMPUTING

Citation Formats

Buckler, Mark, Burleson, Wayne P., and Manne, Srilatha. Methods and systems of synchronizer selection. United States: N. p., 2016. Web.
Buckler, Mark, Burleson, Wayne P., & Manne, Srilatha. Methods and systems of synchronizer selection. United States.
Buckler, Mark, Burleson, Wayne P., and Manne, Srilatha. Tue . "Methods and systems of synchronizer selection". United States. https://www.osti.gov/servlets/purl/1532154.
@article{osti_1532154,
title = {Methods and systems of synchronizer selection},
author = {Buckler, Mark and Burleson, Wayne P. and Manne, Srilatha},
abstractNote = {A circuit includes a plurality of synchronizers to adapt a signal from a first clock domain to a second clock domain. Each synchronizer of the plurality of synchronizers includes a synchronizer input to receive the signal from the first clock domain and a synchronizer output to provide the signal as adapted to the second clock domain. The circuit also includes a multiplexer (mux) that includes a plurality of mux inputs and a mux output. Each mux input is coupled to the synchronizer output of a respective synchronizer of the plurality of synchronizers. The mux output provides the signal, as adapted to the second clock domain, from the synchronizer output of a selected synchronizer of the plurality of synchronizers.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2016},
month = {3}
}

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Works referenced in this record:

Detecting and isolating errors occurring in data communication in a multiple processor system
patent, November 2000


Network router integrated onto a silicon chip
patent, January 2008


Multi-reference clock synchronization techniques
patent, March 2013


Phase detector for a programmable clock synchronizer
patent, March 2005