Title: Methods and systems of synchronizer selection

Abstract

A circuit includes a plurality of synchronizers to adapt a signal from a first clock domain to a second clock domain. Each synchronizer of the plurality of synchronizers includes a synchronizer input to receive the signal from the first clock domain and a synchronizer output to provide the signal as adapted to the second clock domain. The circuit also includes a multiplexer (mux) that includes a plurality of mux inputs and a mux output. Each mux input is coupled to the synchronizer output of a respective synchronizer of the plurality of synchronizers. The mux output provides the signal, as adapted to the second clock domain, from the synchronizer output of a selected synchronizer of the plurality of synchronizers.

Inventors:

Buckler, Mark; Burleson, Wayne P.; Manne, Srilatha

Issue Date:

Tue Mar 22 00:00:00 EDT 2016

Research Org.:

Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1532154

Patent Number(s):

9294263

Application Number:

14/146,654

Assignee:

Advanced Micro Devices, Inc. (Sunnyvale, CA)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04J - MULTIPLEX COMMUNICATION

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F1/10 - Distribution of clock signals {, e.g. skew}
G06F1/12 - Synchronisation of different clock signals {provided by a plurality of clock generators}

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04J - MULTIPLEX COMMUNICATION

H04J3/0602 - {Systems characterised by the synchronising information used}
H04J3/0632 - {Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
H04J3/0638 - {Clock or time synchronisation among nodes
H04J3/0685 - {Clock or time synchronisation in a node

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION

H04L7/02 - Speed or phase control by the received code signals, the signals containing no special synchronisation information {
H04L7/0331 - {with a digital phase-locked loop [PLL] processing binay samples, e.g. add/subtract logic for correction of receiver clock

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04W - WIRELESS COMMUNICATION NETWORKS

H04W56/001 - {Synchronization between nodes}

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DOE Contract Number:  

AC52-07NA27344; B600716

Resource Type:

Patent

Resource Relation:

Patent File Date: 2014-01-02

Country of Publication:

United States

Language:

English

Subject:

42 ENGINEERING; 97 MATHEMATICS AND COMPUTING