High-density latch arrays

Sinangil, Mahmut Ersin; Poulton, John W.; Khailany, Brucek Kurdo; Edmondson, John H.

Title: High-density latch arrays

Abstract

A system and device are provided for implementing memory arrays using high-density latch cells. The device includes an array of cells arranged into columns and rows. Each cell comprises a latch cell that includes a transmission gate, a pair of inverters, and an output buffer. Each row of latch cells is connected to at least one common node for addressing the row of latch cells, and each column of latch cells is connected to a particular bit of an input signal and a particular bit of an output signal. A register file may be implemented using one or more arrays of the high-density latch cells to replace any or all of the banks of SRAM cells typically used to implement the register file.

Inventors:: Sinangil, Mahmut Ersin; Poulton, John W.; Khailany, Brucek Kurdo; Edmondson, John H.

Issue Date:: 2016-01-26

Research Org.:: NVIDIA Corp., Santa Clara, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1532145

Patent Number(s):: 9245601

Application Number:: 14/296,320

Assignee:: NVIDIA Corporation (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

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G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C11/418 - Address circuits
G11C11/419 - Read-write [R-W] circuits
G11C7/106 - {Data output latches}
G11C8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H01L27/0207 - {Geometrical layout of the components, e.g. computer aided design

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DOE Contract Number:: B599861

Resource Type:: Patent

Resource Relation:: Patent File Date: 2014-06-04

Country of Publication:: United States

Language:: English

Citation Formats


                    Sinangil, Mahmut Ersin, Poulton, John W., Khailany, Brucek Kurdo, and Edmondson, John H.. High-density latch arrays.  United States: N. p., 2016. 
        Web.

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                    Sinangil, Mahmut Ersin, Poulton, John W., Khailany, Brucek Kurdo, & Edmondson, John H.. High-density latch arrays.  United States.

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                    Sinangil, Mahmut Ersin, Poulton, John W., Khailany, Brucek Kurdo, and Edmondson, John H.. Tue .  
        "High-density latch arrays".  United States.  https://www.osti.gov/servlets/purl/1532145.

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@article{osti_1532145,

  title        = {High-density latch arrays},

  author       = {Sinangil, Mahmut Ersin and Poulton, John W. and Khailany, Brucek Kurdo and Edmondson, John H.},

  abstractNote = {A system and device are provided for implementing memory arrays using high-density latch cells. The device includes an array of cells arranged into columns and rows. Each cell comprises a latch cell that includes a transmission gate, a pair of inverters, and an output buffer. Each row of latch cells is connected to at least one common node for addressing the row of latch cells, and each column of latch cells is connected to a particular bit of an input signal and a particular bit of an output signal. A register file may be implemented using one or more arrays of the high-density latch cells to replace any or all of the banks of SRAM cells typically used to implement the register file.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2016},

  month        = {1}

}

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Works referenced in this record:

Memory having power saving mode
patent, February 2015

Chen, Wang-Kun; Chong, Yew Keong; Thyagarajan, Sriram
US Patent Document 8,947,968
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8947968

Semiconductor storage device
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Sasaki, Hirotoshi
US Patent Document 7,889,576
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7889576

Multi-port register file with multiplexed data
patent, September 2014

Pelley, Perry H.; Ramaraju, Ravindraraj; Russell, Andrew C.
US Patent Document 8,837,205
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8837205

Semiconductor memory
patent, March 2014

Ishikura, Satoshi; Sumitani, Norihiko
US Patent Document 8,665,637
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8665637

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Title: High-density latch arrays

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Citation Formats

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