System and method for performing address-based SRAM access assists
Abstract
A method and a system are provided for performing address-based memory access assist. An address is received for a memory access and a determination is made, based on the address, that access assist is enabled for at least one storage cell corresponding to the address. The access assist is applied to the at least one storage cell to perform the memory access.
- Inventors:
- Issue Date:
- Research Org.:
- NVIDIA Corp., Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1532141
- Patent Number(s):
- 9208900
- Application Number:
- 14/147,411
- Assignee:
- NVIDIA Corporation (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
- DOE Contract Number:
- B599861; HR0011-13-3-0001
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2014-01-03
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Sinangil, Mahmut Ersin, and Dally, William J. System and method for performing address-based SRAM access assists. United States: N. p., 2015.
Web.
Sinangil, Mahmut Ersin, & Dally, William J. System and method for performing address-based SRAM access assists. United States.
Sinangil, Mahmut Ersin, and Dally, William J. Tue .
"System and method for performing address-based SRAM access assists". United States. https://www.osti.gov/servlets/purl/1532141.
@article{osti_1532141,
title = {System and method for performing address-based SRAM access assists},
author = {Sinangil, Mahmut Ersin and Dally, William J.},
abstractNote = {A method and a system are provided for performing address-based memory access assist. An address is received for a memory access and a determination is made, based on the address, that access assist is enabled for at least one storage cell corresponding to the address. The access assist is applied to the at least one storage cell to perform the memory access.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2015},
month = {12}
}
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Works referencing / citing this record:
Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits
patent, July 2018
- Walker, Darryl G.
- US Patent Document 10,014,049
Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits
patent, August 2018
- Walker, Darryl G.
- US Patent Document 10,049,727
Noise immune data path scheme for multi-bank memory architecture
patent, November 2018
- Narasimhan, Mukund; Gupta, Sharad; Shanmugasundaram, Dharaneedharan
- US Patent Document 10,140,224
Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor
patent, December 2018
- Walker, Darryl G.
- US Patent Document 10,163,524
Voltage-aware adaptive static random access memory (SRAM) write assist circuit
patent, November 2016
- Hunt-Schroeder, Eric D.; Fifield, John A.; Anand, Darren L.
- US Patent Document 9,508,420
Boost control to improve SRAM write operation
patent, January 2017
- Braceras, George M.; Bringivijayaraghavan, Venkatraghavan; Rengarajan, Krishnan S.
- US Patent Document 9,548,104
Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits
patent, April 2018
- Walker, Darryl G.
- US Patent Document 9,940,999