System and method for performing SRAM write assist
Abstract
A method and a system are provided for performing write assist. Write assist circuitry is initialized and voltage collapse is initiated to reduce a column supply voltage provided to a storage cell. A bitline of the storage cell is boosted to a boosted voltage level that is below a low supply voltage provided to the storage cell and data encoded by the bitline is written to the storage cell.
- Inventors:
- Issue Date:
- Research Org.:
- NVIDIA Corp., Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1532132
- Patent Number(s):
- 8861290
- Application Number:
- 13/710,314
- Assignee:
- NVIDIA Corporation (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
- DOE Contract Number:
- B599861
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2012-12-10
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Zimmer, Brian Matthew, and Sinangil, Mahmut Ersin. System and method for performing SRAM write assist. United States: N. p., 2014.
Web.
Zimmer, Brian Matthew, & Sinangil, Mahmut Ersin. System and method for performing SRAM write assist. United States.
Zimmer, Brian Matthew, and Sinangil, Mahmut Ersin. Tue .
"System and method for performing SRAM write assist". United States. https://www.osti.gov/servlets/purl/1532132.
@article{osti_1532132,
title = {System and method for performing SRAM write assist},
author = {Zimmer, Brian Matthew and Sinangil, Mahmut Ersin},
abstractNote = {A method and a system are provided for performing write assist. Write assist circuitry is initialized and voltage collapse is initiated to reduce a column supply voltage provided to a storage cell. A bitline of the storage cell is boosted to a boosted voltage level that is below a low supply voltage provided to the storage cell and data encoded by the bitline is written to the storage cell.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {10}
}
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Works referenced in this record:
Configuration Context Switcher
patent-application, April 2011
- Chandler, Travis; Redgrave, Jason; Voogel, Martin
- US Patent Application 12/676892; 20110089970
Works referencing / citing this record:
Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits
patent, July 2018
- Walker, Darryl G.
- US Patent Document 10,014,049
Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits
patent, August 2018
- Walker, Darryl G.
- US Patent Document 10,049,727
Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor
patent, December 2018
- Walker, Darryl G.
- US Patent Document 10,163,524
Write assist circuit integrated with leakage reduction circuit of a static random access memory for increasing the low voltage supply during write operations
patent, January 2017
- Akhilesh, Ashish; Malviya, Yogesh; Bhatia, Prakash Ravikumar
- US Patent Document 9,542,998
Boost charge recycle for low-power memory
patent, January 2018
- Sinha, Rakesh Kumar; Mathuria, Priyankar; Gupta, Sharad
- US Patent Document 9,875,790
Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits
patent, April 2018
- Walker, Darryl G.
- US Patent Document 9,940,999