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Title: Optimizing TLB entries for mixed page size storage in contiguous memory

Abstract

A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.

Inventors:
; ; ; ; ; ;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1532129
Patent Number(s):
8,856,490
Application Number:
13/618,730
Assignee:
International Business Machines Corporation (Armonk, NY)
DOE Contract Number:  
B554331
Resource Type:
Patent
Resource Relation:
Patent File Date: 2012-09-14
Country of Publication:
United States
Language:
English

Citation Formats

Chen, Dong, Gara, Alan, Giampapa, Mark E., Heidelberger, Philip, Kriegel, Jon K., Ohmacht, Martin, and Steinmacher-Burow, Burkhard. Optimizing TLB entries for mixed page size storage in contiguous memory. United States: N. p., 2014. Web.
Chen, Dong, Gara, Alan, Giampapa, Mark E., Heidelberger, Philip, Kriegel, Jon K., Ohmacht, Martin, & Steinmacher-Burow, Burkhard. Optimizing TLB entries for mixed page size storage in contiguous memory. United States.
Chen, Dong, Gara, Alan, Giampapa, Mark E., Heidelberger, Philip, Kriegel, Jon K., Ohmacht, Martin, and Steinmacher-Burow, Burkhard. Tue . "Optimizing TLB entries for mixed page size storage in contiguous memory". United States. https://www.osti.gov/servlets/purl/1532129.
@article{osti_1532129,
title = {Optimizing TLB entries for mixed page size storage in contiguous memory},
author = {Chen, Dong and Gara, Alan and Giampapa, Mark E. and Heidelberger, Philip and Kriegel, Jon K. and Ohmacht, Martin and Steinmacher-Burow, Burkhard},
abstractNote = {A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {10}
}

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Works referenced in this record:

TLB parity error recovery
patent, May 2005


Block address translation circuit using two-bit to four-bit encoder
patent, May 1999


Optimized scalable network switch
patent, December 2007