Optimizing TLB entries for mixed page size storage in contiguous memory

Title: Optimizing TLB entries for mixed page size storage in contiguous memory

Abstract

A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.

Inventors:: Chen, Dong; Gara, Alan; Giampapa, Mark E.; Heidelberger, Philip; Kriegel, Jon K.; Ohmacht, Martin; Steinmacher-Burow, Burkhard

Issue Date:: 2014-10-07

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1532129

Patent Number(s):: 8856490

Application Number:: 13/618,730

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F2212/652 - Page size control
G06F2212/654 - Look-ahead translation
G06F12/1027 - using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

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DOE Contract Number:: B554331

Resource Type:: Patent

Resource Relation:: Patent File Date: 2012-09-14

Country of Publication:: United States

Language:: English

Citation Formats


                    Chen, Dong, Gara, Alan, Giampapa, Mark E., Heidelberger, Philip, Kriegel, Jon K., Ohmacht, Martin, and Steinmacher-Burow, Burkhard. Optimizing TLB entries for mixed page size storage in contiguous memory.  United States: N. p., 2014. 
        Web.

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                    Chen, Dong, Gara, Alan, Giampapa, Mark E., Heidelberger, Philip, Kriegel, Jon K., Ohmacht, Martin, & Steinmacher-Burow, Burkhard. Optimizing TLB entries for mixed page size storage in contiguous memory.  United States.

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                    Chen, Dong, Gara, Alan, Giampapa, Mark E., Heidelberger, Philip, Kriegel, Jon K., Ohmacht, Martin, and Steinmacher-Burow, Burkhard. Tue .  
        "Optimizing TLB entries for mixed page size storage in contiguous memory".  United States.  https://www.osti.gov/servlets/purl/1532129.

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@article{osti_1532129,

  title        = {Optimizing TLB entries for mixed page size storage in contiguous memory},

  author       = {Chen, Dong and Gara, Alan and Giampapa, Mark E. and Heidelberger, Philip and Kriegel, Jon K. and Ohmacht, Martin and Steinmacher-Burow, Burkhard},

  abstractNote = {A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2014},

  month        = {10}

}

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Works referenced in this record:

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Similar Records

Title: Optimizing TLB entries for mixed page size storage in contiguous memory

Abstract

Citation Formats

System and Method for Cache-Locking Mechanism Using Translation Table Attributes for Replacement Class ID Determination patent-application, January 2009

Multi-Petascale Highly Efficient Parallel Supercomputer patent-application, September 2011

TLB parity error recovery patent, May 2005

Block address translation circuit using two-bit to four-bit encoder patent, May 1999

Mapping an arbitrary number of contiguous memory pages at an arbitrary alignment patent, February 2007

Translation look-aside buffer with variable page sizes patent, April 2012

Method and Apparatus for Efficient Replacement Algorithm for Pre-Fetcher Oriented Data Cache patent-application, December 2008

Optimized scalable network switch patent, December 2007

System and Method for Cache-Locking Mechanism Using Translation Table Attributes for Replacement Class ID Determination
patent-application, January 2009

Multi-Petascale Highly Efficient Parallel Supercomputer
patent-application, September 2011

TLB parity error recovery
patent, May 2005

Block address translation circuit using two-bit to four-bit encoder
patent, May 1999

Mapping an arbitrary number of contiguous memory pages at an arbitrary alignment
patent, February 2007

Translation look-aside buffer with variable page sizes
patent, April 2012

Method and Apparatus for Efficient Replacement Algorithm for Pre-Fetcher Oriented Data Cache
patent-application, December 2008

Optimized scalable network switch
patent, December 2007