Optimizing TLB entries for mixed page size storage in contiguous memory
Abstract
A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1532129
- Patent Number(s):
- 8856490
- Application Number:
- 13/618,730
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- B554331
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2012-09-14
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Chen, Dong, Gara, Alan, Giampapa, Mark E., Heidelberger, Philip, Kriegel, Jon K., Ohmacht, Martin, and Steinmacher-Burow, Burkhard. Optimizing TLB entries for mixed page size storage in contiguous memory. United States: N. p., 2014.
Web.
Chen, Dong, Gara, Alan, Giampapa, Mark E., Heidelberger, Philip, Kriegel, Jon K., Ohmacht, Martin, & Steinmacher-Burow, Burkhard. Optimizing TLB entries for mixed page size storage in contiguous memory. United States.
Chen, Dong, Gara, Alan, Giampapa, Mark E., Heidelberger, Philip, Kriegel, Jon K., Ohmacht, Martin, and Steinmacher-Burow, Burkhard. Tue .
"Optimizing TLB entries for mixed page size storage in contiguous memory". United States. https://www.osti.gov/servlets/purl/1532129.
@article{osti_1532129,
title = {Optimizing TLB entries for mixed page size storage in contiguous memory},
author = {Chen, Dong and Gara, Alan and Giampapa, Mark E. and Heidelberger, Philip and Kriegel, Jon K. and Ohmacht, Martin and Steinmacher-Burow, Burkhard},
abstractNote = {A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {10}
}
Works referenced in this record:
System and Method for Cache-Locking Mechanism Using Translation Table Attributes for Replacement Class ID Determination
patent-application, January 2009
- Burns, Adam Patrick; Dale, Jason Michael; DeMent, Jonathan James
- US Patent Application 11/777331; 20090019252
Multi-Petascale Highly Efficient Parallel Supercomputer
patent-application, September 2011
- Asaad, Sameh; Bellofatto, Ralph E.; Blocksome, Michael A.
- US Patent Document 13/004007; 20110219208
TLB parity error recovery
patent, May 2005
- Griffith, Jr., T. W.; Thatcher, Larry Edward
- US Patent Document 6,901,540
Block address translation circuit using two-bit to four-bit encoder
patent, May 1999
- Martens, David James; Potter, Terence
- US Patent Document 5,907,866
Mapping an arbitrary number of contiguous memory pages at an arbitrary alignment
patent, February 2007
- Hastings, Andrew B.
- US Patent Document 7,181,587
Translation look-aside buffer with variable page sizes
patent, April 2012
- Steiss, Donald E.
- US Patent Document 8,156,309
Method and Apparatus for Efficient Replacement Algorithm for Pre-Fetcher Oriented Data Cache
patent-application, December 2008
- Brunheroto, Jose R.; Salapura, Valentina
- US Patent Application 11/767717; 20080320228
Optimized scalable network switch
patent, December 2007
- Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.
- US Patent Document 7,305,487