Synchronizer circuits with failure-condition detection and correction
Abstract
An input signal and a reset signal are provided to respective inputs of a resettable flip-flop. The resettable flip-flop generates an output signal. The output signal transitions from a first logic state to a second logic state in response to corresponding transitions of the input signal and transitions from the second logic state to the first logic state in response to assertion of the reset signal. A warning signal is asserted in response to transitions of the input signal from the second logic state to the first logic state. A logic gate forwards the output signal when the warning signal is de-asserted and provides a signal in the first logic state in response to assertion of the warning signal.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1532125
- Patent Number(s):
- 8847647
- Application Number:
- 14/024,396
- Assignee:
- Advanced Micro Devices, Inc. (Sunnyvale, CA)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
- DOE Contract Number:
- AC52-07NA27344; B600716
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2013-09-11
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Buckler, Mark. Synchronizer circuits with failure-condition detection and correction. United States: N. p., 2014.
Web.
Buckler, Mark. Synchronizer circuits with failure-condition detection and correction. United States.
Buckler, Mark. Tue .
"Synchronizer circuits with failure-condition detection and correction". United States. https://www.osti.gov/servlets/purl/1532125.
@article{osti_1532125,
title = {Synchronizer circuits with failure-condition detection and correction},
author = {Buckler, Mark},
abstractNote = {An input signal and a reset signal are provided to respective inputs of a resettable flip-flop. The resettable flip-flop generates an output signal. The output signal transitions from a first logic state to a second logic state in response to corresponding transitions of the input signal and transitions from the second logic state to the first logic state in response to assertion of the reset signal. A warning signal is asserted in response to transitions of the input signal from the second logic state to the first logic state. A logic gate forwards the output signal when the warning signal is de-asserted and provides a signal in the first logic state in response to assertion of the warning signal.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {9}
}
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Works referenced in this record:
Aircraft windshear detection based on energy loss
patent, October 1991
- Zweifel, Terry L.; Youssefi, Khosrow H.
- US Patent Document 5,053,767
Compute-centric architecture for integrated circuits
patent, June 2010
- Young, Steven P.; Gaide, Brian C.
- US Patent Document 7,746,108
Output structure with cascaded control signals for logic blocks in integrated circuits, and methods of using the same
patent, June 2010
- Gaide, Brian C.; Young, Steven P.
- US Patent Document 7,746,112
Bus-based logic blocks with optional constant input
patent, July 2011
- Young, Steven P.
- US Patent Document 7,982,496
Multiplier circuits with optional shift function
patent, April 2014
- Young, Steven P.
- US Patent Document 8,706,793
Method and apparatus for protecting, optimizing, and reporting synchronizers
patent, May 2014
- Fung, Ryan; Betz, Vaughn Timothy; Neto, David
- US Patent Document 8,732,639
Apparatus and Method for Synchronising Signals
patent-application, November 2013
- Kulmala, Ari Tapanio; Qu, Yang
- US Patent Application 13/746103; 20130314134
System and Method for Determining a Time for Safely Sampling a Signal of a Clock Domain
patent-application, August 2013
- Dally, William J.; Tell, Stephen G.
- US Patent Application 13/849414; 20130216013
Propagation Simulator Buffer
patent-application, March 2014
- Osborn, Michael J.; Tresidder, Michale J.; Grenat, Aaron J.
- US Patent Application 14/076020; 20140062555
Interfaces, Circuits, and Methods for Communicating with a Double Data Rate Memory Device
patent-application, March 2011
- Linam, Daivd; Haugestuen, Benjamin P.; Evans, Scott T.
- US Patent Application 12/557658; 20110063931
High-Resolution Phase Detector
patent-application, May 2014
- Dally, William J.; Tell, Stephen G.
- US Patent Application 13/676021; 20140132245
System for checking clock-signal correspondence
patent-application, November 2007
- Gilday, David Michael; Bradley, Daryl Wayne; Ashfield, Edmond John Simon
- US Patent Application 11/414551; 20070255974