Synchronizer circuits with failure-condition detection and correction
Abstract
An input signal and a reset signal are provided to respective inputs of a resettable flip-flop. The resettable flip-flop generates an output signal. The output signal transitions from a first logic state to a second logic state in response to corresponding transitions of the input signal and transitions from the second logic state to the first logic state in response to assertion of the reset signal. A warning signal is asserted in response to transitions of the input signal from the second logic state to the first logic state. A logic gate forwards the output signal when the warning signal is de-asserted and provides a signal in the first logic state in response to assertion of the warning signal.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1532125
- Patent Number(s):
- 8,847,647
- Application Number:
- 14/024,396
- Assignee:
- Advanced Micro Devices, Inc. (Sunnyvale, CA)
- DOE Contract Number:
- AC52-07NA27344; B600716
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2013-09-11
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Buckler, Mark. Synchronizer circuits with failure-condition detection and correction. United States: N. p., 2014.
Web.
Buckler, Mark. Synchronizer circuits with failure-condition detection and correction. United States.
Buckler, Mark. Tue .
"Synchronizer circuits with failure-condition detection and correction". United States. https://www.osti.gov/servlets/purl/1532125.
@article{osti_1532125,
title = {Synchronizer circuits with failure-condition detection and correction},
author = {Buckler, Mark},
abstractNote = {An input signal and a reset signal are provided to respective inputs of a resettable flip-flop. The resettable flip-flop generates an output signal. The output signal transitions from a first logic state to a second logic state in response to corresponding transitions of the input signal and transitions from the second logic state to the first logic state in response to assertion of the reset signal. A warning signal is asserted in response to transitions of the input signal from the second logic state to the first logic state. A logic gate forwards the output signal when the warning signal is de-asserted and provides a signal in the first logic state in response to assertion of the warning signal.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {9}
}
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