Balanced charge-recycling repeater link
Abstract
A balanced, charge-recycling repeater link is disclosed. The link includes a first set of segments operating in a first voltage domain and a second set of segments operating in a second voltage domain. The link is configured to transmit a first signal over at least one segment in the first set of segments and at least one other segment in the second set of segments. Each segment of the link includes at least one active circuit element configured to charge or discharge one or more corresponding interconnects within the link and a level shifter configured to shift the level of a signal on a last interconnect of the segment from the first voltage domain to the second voltage domain or the second voltage domain to the first voltage domain.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Defense Advanced Research Projects Agency
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1532084
- Patent Number(s):
- 9954527
- Application Number:
- 14/869,759
- Assignee:
- NVIDIA Corporation (Santa Clara, CA)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
- DOE Contract Number:
- B609478; HR0011-13-3-0001
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2015-09-29
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Wilson, John Michael, Poulton, John W., Fojtik, Matthew Rudolph, and Gray, Carl Thomas. Balanced charge-recycling repeater link. United States: N. p., 2018.
Web.
Wilson, John Michael, Poulton, John W., Fojtik, Matthew Rudolph, & Gray, Carl Thomas. Balanced charge-recycling repeater link. United States.
Wilson, John Michael, Poulton, John W., Fojtik, Matthew Rudolph, and Gray, Carl Thomas. Tue .
"Balanced charge-recycling repeater link". United States. https://www.osti.gov/servlets/purl/1532084.
@article{osti_1532084,
title = {Balanced charge-recycling repeater link},
author = {Wilson, John Michael and Poulton, John W. and Fojtik, Matthew Rudolph and Gray, Carl Thomas},
abstractNote = {A balanced, charge-recycling repeater link is disclosed. The link includes a first set of segments operating in a first voltage domain and a second set of segments operating in a second voltage domain. The link is configured to transmit a first signal over at least one segment in the first set of segments and at least one other segment in the second set of segments. Each segment of the link includes at least one active circuit element configured to charge or discharge one or more corresponding interconnects within the link and a level shifter configured to shift the level of a signal on a last interconnect of the segment from the first voltage domain to the second voltage domain or the second voltage domain to the first voltage domain.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {4}
}
Works referenced in this record:
Level shifting circuit
patent, October 2008
- Bajkowski, Maciej; Hoekstra, George P.; Ghassemi, Hamed
- US Patent Document 7,443,223
Single supply level shifter circuit for multi-voltage designs, capable of up/down shifting
patent, July 2010
- Ali, Shahid; Manohar, Sujan Kundapur
- US Patent Document 7,750,717
Method and apparatus for voltage level shifting with concurrent synchronization
patent, October 2012
- Ng, Ju Tung; Fung, Richard; Lau, Ricky
- US Patent Document 8,278,969
Level shifter for an input/output bus in a CMOS dynamic ram
patent, August 1989
- Choi, Yun-Ho
- US Patent Document 4,860,257
Level shifter circuit to shift signals from a logic voltage to an input/output voltage
patent, August 2010
- Lin, Hwong-Kwo; Yang, Ge; Ning, Guoqing
- US Patent Document 7,772,885
Self-tuning of signal path delay in circuit employing multiple voltage domains
patent, January 2011
- Chai, Chiaming; Liles, Stephen Edward
- US Patent Document 7,876,631
Reducing minimum operating voltage through hybrid cache design
patent, October 2014
- Khellah, Muhammad M.; Wilkerson, Christopher B.; Alameldeen, Alaa R.
- US Patent Document 8,868,836
Low power single rail input voltage level shifter
patent, November 2010
- Yang, Ge; Lin, Hwong-Kwo; Young, Charles Chew-Yuen
- US Patent Document 7,839,170
Low voltage signaling
patent, January 2014
- Chang, Leland; Dennard, Robert H.; Ji, Brian L.
- US Patent Document 8,629,705
Charge-recycling voltage domains for energy-efficient low-voltage operation of digital CMOS circuits
patent, February 2008
- Shepard, Kenneth L.; Rajapandian, Saravanan
- US Patent Document 7,329,968
Stacked clock distribution for low power devices
patent, February 2015
- Kapoor, Ajay; Malzahn, Ralf; Meijer, Rinze Ida Mechtildis Peter
- US Patent Document 8,947,149
Calibration schemes for charge-recycling stacked voltage domains
patent, August 2014
- Friedman, Daniel J.; Liu, Yong; Tierno, Jose A.
- US Patent Document 8,797,084