skip to main content
DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Thermal aware data placement and compute dispatch in a memory system

Abstract

A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.

Inventors:
; ; ; ;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1532082
Patent Number(s):
9947386
Application Number:
14/492,045
Assignee:
Advanced Micro Devices, Inc. (Sunnyvale, CA)
Patent Classifications (CPCs):
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
DOE Contract Number:  
AC52-07NA27344; B600716
Resource Type:
Patent
Resource Relation:
Patent File Date: 2014-09-21
Country of Publication:
United States
Language:
English

Citation Formats

Arora, Manish, Paul, Indrani, Eckert, Yasuko, Jayasena, Nuwan, and Zhang, Dong Ping. Thermal aware data placement and compute dispatch in a memory system. United States: N. p., 2018. Web.
Arora, Manish, Paul, Indrani, Eckert, Yasuko, Jayasena, Nuwan, & Zhang, Dong Ping. Thermal aware data placement and compute dispatch in a memory system. United States.
Arora, Manish, Paul, Indrani, Eckert, Yasuko, Jayasena, Nuwan, and Zhang, Dong Ping. Tue . "Thermal aware data placement and compute dispatch in a memory system". United States. https://www.osti.gov/servlets/purl/1532082.
@article{osti_1532082,
title = {Thermal aware data placement and compute dispatch in a memory system},
author = {Arora, Manish and Paul, Indrani and Eckert, Yasuko and Jayasena, Nuwan and Zhang, Dong Ping},
abstractNote = {A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {4}
}

Patent:

Save / Share:

Works referenced in this record:

Hybrid drive migrating high workload data from disk to non-volatile semiconductor memory
patent, February 2016


Dynamic Management of Thermal Loads
patent-application, November 2013


TOP-PIM: throughput-oriented programmable processing in memory
conference, January 2014

  • Zhang, Dongping; Jayasena, Nuwan; Lyashevsky, Alexander
  • Proceedings of the 23rd international symposium on High-performance parallel and distributed computing - HPDC '14
  • https://doi.org/10.1145/2600212.2600213

Integrated calibration apparatus for a multi-mode information storage system
patent, November 1999


Disk drive that positions a head at multiple head-to-disk spacings
patent, January 2008


Variable refresh control for a memory
patent, August 2004


Memory device and method of accessing a memory device
patent, October 2004


Transparent continuous refresh RAM cell architecture
patent, August 2002


A survey of architectural techniques for DRAM power management
journal, January 2012


System-on-chip with memory speed control core
patent, May 2013


Thermal modeling and management of DRAM memory systems
conference, January 2007


Interface for solid-state memory
patent, April 2012


Memory Data Management
patent-application, December 2014


Method for adaptive formatting and track traversal in data storage devices
patent, October 2000


System and method for adaptively configuring an L2 cache memory mesh
patent, April 2014


System and method for selective memory module power management
patent, September 2008


Dynamic DASD data management and partitioning based on access frequency utilization and capacity
patent, November 2001


A comprehensive study of energy efficiency and performance of flash-based SSD
journal, April 2011


Apparatus and method for a memory unit with a processor integrated therein
patent, October 1997


Multiple class memory systems
patent, January 2015