Thermal aware data placement and compute dispatch in a memory system

Arora, Manish; Paul, Indrani; Eckert, Yasuko; Jayasena, Nuwan; Zhang, Dong Ping

Advanced Search OptionsAdvanced Search queries use a traditional Term Search. For more info, see our FAQ.

All Fields:

Patent Title:

Abstract:

Assignee:

Inventor(s):

Patent Number:

Patent Classification (CPC):

All Classifications
A - human necessities
A01 - agriculture
A21 - baking
A22 - butchering
A23 - foods or foodstuffs
A24 - tobacco
A41 - wearing apparel
A42 - headwear
A43 - footwear
A44 - haberdashery
A45 - hand or travelling articles
A46 - brushware
A47 - furniture
A61 - medical or veterinary science
A62 - life-saving
A63 - sports
A99 - subject matter not otherwise provided for in this section
B - performing operations
B01 - physical or chemical processes or apparatus in general
B02 - crushing, pulverising, or disintegrating
B03 - separation of solid materials using liquids or using pneumatic tables or jigs
B04 - centrifugal apparatus or machines for carrying-out physical or chemical processes
B05 - spraying or atomising in general
B06 - generating or transmitting mechanical vibrations in general
B07 - separating solids from solids
B08 - cleaning
B09 - disposal of solid waste
B21 - mechanical metal-working without essentially removing material
B22 - casting
B23 - machine tools
B24 - grinding
B25 - hand tools
B26 - hand cutting tools
B27 - working or preserving wood or similar material
B28 - working cement, clay, or stone
B29 - working of plastics
B30 - presses
B31 - making articles of paper, cardboard or material worked in a manner analogous to paper
B32 - layered products
B33 - additive manufacturing technology
B41 - printing
B42 - bookbinding
B43 - writing or drawing implements
B44 - decorative arts
B60 - vehicles in general
B61 - railways
B62 - land vehicles for travelling otherwise than on rails
B63 - ships or other waterborne vessels
B64 - aircraft
B65 - conveying
B66 - hoisting
B67 - opening, closing {or cleaning} bottles, jars or similar containers
B68 - saddlery
B81 - microstructural technology
B82 - nanotechnology
B99 - subject matter not otherwise provided for in this section
C - chemistry
C01 - inorganic chemistry
C02 - treatment of water, waste water, sewage, or sludge
C03 - glass
C04 - cements
C05 - fertilisers
C06 - explosives
C07 - organic chemistry
C08 - organic macromolecular compounds
C09 - dyes
C10 - petroleum, gas or coke industries
C11 - animal or vegetable oils, fats, fatty substances or waxes
C12 - biochemistry
C13 - sugar industry
C14 - skins
C21 - metallurgy of iron
C22 - metallurgy
C23 - coating metallic material
C25 - electrolytic or electrophoretic processes
C30 - crystal growth
C40 - combinatorial technology
C99 - subject matter not otherwise provided for in this section
D - textiles
D01 - natural or man-made threads or fibres
D02 - yarns
D03 - weaving
D04 - braiding
D05 - sewing
D06 - treatment of textiles or the like
D07 - ropes
D10 - indexing scheme associated with sublasses of section d, relating to textiles
D21 - paper-making
D99 - subject matter not otherwise provided for in this section
E - fixed constructions
E01 - construction of roads, railways, or bridges
E02 - hydraulic engineering
E03 - water supply
E04 - building
E05 - locks
E06 - doors, windows, shutters, or roller blinds in general
E21 - earth drilling
E99 - subject matter not otherwise provided for in this section
F - mechanical engineering
F01 - machines or engines in general
F02 - combustion engines
F03 - machines or engines for liquids
F04 - positive - displacement machines for liquids
F05 - indexing schemes relating to engines or pumps in various subclasses of classes f01-f04
F15 - fluid-pressure actuators
F16 - engineering elements and units
F17 - storing or distributing gases or liquids
F21 - lighting
F22 - steam generation
F23 - combustion apparatus
F24 - heating
F25 - refrigeration or cooling
F26 - drying
F27 - furnaces
F28 - heat exchange in general
F41 - weapons
F42 - ammunition
F99 - subject matter not otherwise provided for in this section
G - physics
G01 - measuring
G02 - optics
G03 - photography
G04 - horology
G05 - controlling
G06 - computing
G07 - checking-devices
G08 - signalling
G09 - education
G10 - musical instruments
G11 - information storage
G12 - instrument details
G16 - information and communication technology [ict] specially adapted for specific application fields
G21 - nuclear physics
G99 - subject matter not otherwise provided for in this section
H - electricity
H01 - basic electric elements
H02 - generation
H03 - basic electronic circuitry
H04 - electric communication technique
H05 - electric techniques not otherwise provided for
H99 - subject matter not otherwise provided for in this section
Y - new / cross sectional technologies
Y02 - technologies or applications for mitigation or adaptation against climate change
Y04 - information or communication technologies having an impact on other technology areas
Y10 - technical subjects covered by former uspc

More Options ...

Title: Thermal aware data placement and compute dispatch in a memory system

Abstract

A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.

Inventors:: Arora, Manish; Paul, Indrani; Eckert, Yasuko; Jayasena, Nuwan; Zhang, Dong Ping

Issue Date:: 2018-04-17

Research Org.:: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1532082

Patent Number(s):: 9947386

Application Number:: 14/492,045

Assignee:: Advanced Micro Devices, Inc. (Sunnyvale, CA)

Patent Classifications (CPCs):: G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES

Show more

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G11C5/025 - {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
G11C7/04 - with means for avoiding disturbances due to temperature effects
G11C8/12 - Group selection circuits, e.g. for memory block selections, chip selection, array selection

Show less

DOE Contract Number:: AC52-07NA27344; B600716

Resource Type:: Patent

Resource Relation:: Patent File Date: 2014-09-21

Country of Publication:: United States

Language:: English

Citation Formats


                    Arora, Manish, Paul, Indrani, Eckert, Yasuko, Jayasena, Nuwan, and Zhang, Dong Ping. Thermal aware data placement and compute dispatch in a memory system.  United States: N. p., 2018. 
        Web.

Copy to clipboard


                    Arora, Manish, Paul, Indrani, Eckert, Yasuko, Jayasena, Nuwan, & Zhang, Dong Ping. Thermal aware data placement and compute dispatch in a memory system.  United States.

Copy to clipboard


                    Arora, Manish, Paul, Indrani, Eckert, Yasuko, Jayasena, Nuwan, and Zhang, Dong Ping. Tue .  
        "Thermal aware data placement and compute dispatch in a memory system".  United States.  https://www.osti.gov/servlets/purl/1532082.

Copy to clipboard


                    
@article{osti_1532082,

  title        = {Thermal aware data placement and compute dispatch in a memory system},

  author       = {Arora, Manish and Paul, Indrani and Eckert, Yasuko and Jayasena, Nuwan and Zhang, Dong Ping},

  abstractNote = {A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2018},

  month        = {4}

}

Copy to clipboard

Patent:

Save / Share:

Export Metadata

Save to My Library

Works referenced in this record:

Hybrid drive migrating high workload data from disk to non-volatile semiconductor memory
patent, February 2016

Wilkins, Virgil V.; Fallone, Robert M.; Meyer, Alan T.
US Patent Document 9,268,499
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9268499

Thermally-Aware Process Scheduling
patent-application, August 2015

Paul, Indrani; Arora, Manish; Bircher, William Lloyd
US Patent Application 14/180023; 20150227391
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20150227391

Methods and apparatuses for heat management in information systems
patent-application, March 2009

Arakawa, Hiroshi; Kano, Yoshiki
US Patent Application 12/068944; 20090077558
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090077558

Storage System, Storage Apparatus, Control Methods of Storage System, and Computer Product
patent-application, October 2014

Tamura, Masahisa
US Patent Application 14/174890; 20140297947
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140297947

Dynamic Management of Thermal Loads
patent-application, November 2013

Lefurgy, Charles Robert; Rawson, III, Freeman Leigh; Silva, Guillermo Jesus
US Patent Application 13/468923; 20130305067
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130305067

TOP-PIM: throughput-oriented programmable processing in memory
conference, January 2014

Zhang, Dongping; Jayasena, Nuwan; Lyashevsky, Alexander
Proceedings of the 23rd international symposium on High-performance parallel and distributed computing - HPDC '14
https://doi.org/10.1145/2600212.2600213

Memory Storage Device, Memory Controller, and Temperature Management Method
patent-application, March 2013

Chu, Chien-Hua
US Patent Application 13/297280; 20130080680
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130080680

Hybrid Storage Aggregate Block Tracking
patent-application, September 2013

Chang, Koling; Sundaram, Rajesh; Doucette, Douglas P.
US Patent Application 13/413877; 20130238851
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130238851

Systems and Methods for Memory System Management Based on Thermal Information of a Memory System
patent-application, September 2014

Walker, Robert; Roberts, David A.
US Patent Application 14/055672; 20140281311
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140281311

Integrated calibration apparatus for a multi-mode information storage system
patent, November 1999

Clark, Alan Robert; Hutchins, Robert A.; Jaquette, Glen Alan
US Patent Document 5,978,335
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5978335

Storage Device and Global Garbage Collection Method of Data Storage System Including the Same
patent-application, December 2014

Lee, Sang-Geol; Lee, Wonju
US Patent Application 14/244039; 20140372698
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140372698

Data Storage Device
patent-application, September 2009

Aoki, Jun
US Patent Application 12/393773; 20090225461
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090225461

Disk drive that positions a head at multiple head-to-disk spacings
patent, January 2008

Schreck, Erhard; Brunnett, Donald; Yu, Jingbo
US Patent Document 7,324,299
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7324299

Disc drive apparatus
patent-application, May 2006

Van Der Kall, Herman Petrus
US Patent Application 10/541986; 20060092801
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060092801

Power Control in a Dispersed Storage Network
patent-application, October 2014

Volvovski, Ilya; Gladwin, S. Christopher; Grube, Gary W.
US Patent Application 14/172218; 20140298061
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140298061

Variable refresh control for a memory
patent, August 2004

Burgan, John M.
US Patent Document 6,778,457
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6778457

Memory device and method of accessing a memory device
patent, October 2004

Schäfer, Andre; Zuckerstatter, Andrea
US Patent Document 6,804,160
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6804160

Storage system and storage control method achieving both power saving and good performance
patent-application, December 2007

Kakihara, Shinobu; Sato, Mitsuhide
US Patent Application 11/500436; 20070294552
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20070294552

Transparent continuous refresh RAM cell architecture
patent, August 2002

Afghahi, Cyrus; Issa, Sami
US Patent Document 6,430,098
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6430098

Maintaining level heat emission in multiprocessor by rectifying dispatch table assigned with static tasks scheduling using assigned task parameters
patent, January 2011

Maeda, Seiji; Kanai, Tatsunori
US Patent Document 7,877,751
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7877751

A survey of architectural techniques for DRAM power management
journal, January 2012

Mittal, Sparsh
International Journal of High Performance Systems Architecture, Vol. 4, Issue 2
https://doi.org/10.1504/IJHPSA.2012.050990

Arrayed processing element redundancy architecture
patent-application, September 2003

Koob, John Conrad; Sung, Raymond Jit-Hung
US Patent Application 10/395656; 20030179631
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20030179631

System-on-chip with memory speed control core
patent, May 2013

Kraipak, Waseem; Bendak, George Beshara
US Patent Document 8,438,358
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8438358

Dynamic Operations for 3D Stacked Memory Using Thermal Data
patent-application, October 2013

Saraswat, Ruchir; Gries, Matthias
US Patent Application 13/995899; 20130275665
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130275665

Thermal modeling and management of DRAM memory systems
conference, January 2007

Lin, Jiang; Zheng, Hongzhong; Zhu, Zhichun
Proceedings of the 34th annual international symposium on Computer architecture - ISCA '07
https://doi.org/10.1145/1250662.1250701

Interface for solid-state memory
patent, April 2012

Zhou, Wei; Chu, Chee Hoe; Chang, Po-Chien
US Patent Document 8,151,037
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8151037

Dynamic Storage Based on Performance Throttling
patent-application, October 2008

Belady, Christian L.
US Patent Application 11/742094; 20080270691
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080270691

Non-volatile storage subsystem with energy-based performance throttling
patent, July 2014

Horn, Robert L.
US Patent Document 8,788,779
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8788779

Storage Device
patent-application, November 2011

Koseki, Hideyuki
US Patent Application 12/742783; 20110283046
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20110283046

Method and system for utilizing DRAM components in a system-on-chip
patent-application, June 2008

Chen, Kun Lung; Chung, Shine
US Patent Application 11/638596; 20080142860
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080142860

Method and apparatus for using smart memories in computing
patent-application, January 2003

Chung, Shine C.
US Patent Application 10/099440; 20030018868
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20030018868

Memory Subsystem and Computer System
patent-application, January 2014

Fujita, Norio; Hori, Masahiro; Murakami, Masahiro
US Patent Application 13/945330; 20140025855
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140025855

Memory System Connector
patent-application, April 2014

Coteus, Paul W.; Hall, Shawn A.; Hunter, Hillery C.
US Patent Application 13/657058; 20140115281
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140115281

Multi-Level Memory Architecture With Data Prioritization
patent-application, January 2008

Bartley, Gerald K.; Borkenhagen, John M.; Germann, Philip R.
US Patent Application 11/457234; 20080016297
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080016297

Non-volatile memory management
patent-application, August 2007

Cornwell, Michael J.; Dudte, Christopher P.
US Patent Application 11/341252; 20070180186
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20070180186

Apparatus, System and Method for Managing Lifetime of a Storage Device
patent-application, March 2012

Fillingim, Jeremy
US Patent Application 13/272964; 20120066439
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20120066439

Memory Data Management
patent-application, December 2014

Dell, Timothy J.; Dusanapudi, Manoj; Jayaraman, Prasanna
US Patent Application 13/906691; 20140359241
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140359241

Controlling Sprinting for Thermal Capacity Boosted Systems
patent-application, December 2014

Arora, Manish; Jayasena, Nuwan; Schulte, Michael
US Patent Application 13/925269; 20140380329
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140380329

Memory access system, address converter, and address conversion method capable of reducing a memory access time
patent, March 2002

Takizawa, Tetsuro
US Patent Document 6,356,988
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6356988

Online Data Movement Without Compromising Data Integrity
patent-application, March 2016

Verma, Surendra; Paleologa, Emanuel; Hortsch, Erik Gregory
US Patent Application 14/486198; 20160080490
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20160080490

Method for adaptive formatting and track traversal in data storage devices
patent, October 2000

Hetzler, Steven R.; Kasiraj, Prakash; New, Richard M. H.
US Patent Document 6,137,644
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6137644

System and method for adaptively configuring an L2 cache memory mesh
patent, April 2014

Kraipak, Waseem; Bendak, George Beshara
US Patent Document 8,706,966
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8706966

System and method for selective memory module power management
patent, September 2008

Jeddeloh, Joseph M.; Lee, Terry R.
US Patent Document 7,428,644
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7428644

Dynamic DASD data management and partitioning based on access frequency utilization and capacity
patent, November 2001

Christenson, Patrick James; Corrigan, Michael J.; Crowley, Thomas R.
US Patent Document 6,324,620
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6324620

Disk Drive With Multiple Level Power Reduction During Write
patent-application, December 2008

Escobar-Bowser, Priscilla; Wolfe, Mark; Ranmuthu, Indumini Wijayanayake
US Patent Application 11/844934; 20080298186
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080298186

Logical disk management method and apparatus
patent-application, January 2006

Sasamoto, Kyoichi
US Patent Application 11/175319; 20060010290
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060010290

A comprehensive study of energy efficiency and performance of flash-based SSD
journal, April 2011

Park, Seonyeong; Kim, Youngjae; Urgaonkar, Bhuvan
Journal of Systems Architecture, Vol. 57, Issue 4, p. 354-365
https://doi.org/10.1016/j.sysarc.2011.01.005

System and Method for Controlling Various Aspects of PCIe Direct Attached Nonvolatile Memory Storage Subsystems
patent-application, March 2016

Skandakumaran, Krishanth; Medapati, Arun Kumar; Namala, Sri Rama
US Patent Application 14/493560; 20160085458
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20160085458

System, Method and Computer Program Product for Multi-Thread Operation Involving First Memory of a First Memory Class and Second Memory of a Second Memory Class
patent-application, May 2015

Smith, Michael S.
US Patent Application 14/589931; 20150143037
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20150143037

Dynamic updating of thresholds in accordance with operating conditons
patent-application, July 2010

Steinbrecher, Robin; Le, Christian; Khanna, Rabul
US Patent Application 12/317965; 20100169585
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20100169585

Memory Circuitry Including Computational Circuity for Performing Supplemental Functions
patent-application, July 2014

Hyde, Roderick A.; Pasch, Nicholas F.; Tegreene, Clarence T.
US Patent Application 13/841042; 20140208041
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140208041

Thermally Sensitive Wear Leveling for a Flash Memory Device that Includes a Plurality of Flash Memory Modules
patent-application, March 2016

Campbell, Keith M.; Megarity, William M.; Remis, Luke D.
US Patent Application 14/473121; 20160062676
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20160062676

Apparatus and method for a memory unit with a processor integrated therein
patent, October 1997

Pawate, Basavaraj I.; Poteet, Kenneth A.; Neal, Joe H.
US Patent Document 5,678,021
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5678021

Information Processing Apparatus, Control Method Therefor, and Computer-Readable Storage Medium
patent-application, June 2014

Mima, Tsuyoshi
US Patent Application 14/090384; 20140160531
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140160531

Hybrid Storage Device and Method of Operating the Same
patent-application, June 2013

Cheong, Seung Kook
US Patent Application 13/660496; 20130159597
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130159597

Access controller for storage devices
patent-application, April 2005

Williams, James A.; Bridge, William
US Patent Application 10/681618; 20050081009
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20050081009

Multiple class memory systems
patent, January 2015

Smith, Michael
US Patent Document 8,930,647
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8930647

Similar Records in DOE Patents and OSTI.GOV collections:

Method and apparatus for temperature-gradient aware data-placement for 3D stacked DRAMs

Patent Kotra, Jagadish B.; Rao, Karthik; Greathouse, Joseph L.

A system including a stack of two or more layers of volatile memory, such as layers of a 3D stacked DRAM memory, places data in the stack based on a temperature or a refresh rate. When a threshold is exceeded, data are moved from a first region to a second region in the stack, the second region having one or both of a second temperature lower than a first temperature of the first region or a second refresh rate lower than a first refresh rate of the first region.
Full Text Available
Method and apparatus for selective and power-aware memory error protection and memory management

Patent Andrade Costa, Carlos H.; Cher, Chen-Yong; Park, Yoonho; ...

A method for providing selective memory error protection responsive to a predictable failure notification associated with at least one portion of a memory in a computing system includes: obtaining an active error correcting code (ECC) configuration corresponding to the portion of the memory; determining whether the active ECC configuration is sufficient to correct at least one error in the portion of the memory affected by the predictable failure notification; when the active ECC configuration is insufficient to correct the error, determining whether data corruption can be tolerated by an application running on the computing system; when data corruption cannot bemore » « less
Full Text Available
Computer memory management system

Patent Kirk, III, Whitson John (Greenwood, MO)

A computer memory management system utilizing a memory structure system of "intelligent" pointers in which information related to the use status of the memory structure is designed into the pointer. Through this pointer system, The present invention provides essentially automatic memory management (often referred to as garbage collection) by allowing relationships between objects to have definite memory management behavior by use of coding protocol which describes when relationships should be maintained and when the relationships should be broken. In one aspect, the present invention system allows automatic breaking of strong links to facilitate object garbage collection, coupled with relationship adjectivesmore » « less
Full Text Available
Chaining direct memory access data transfer operations for compute nodes in a parallel computer

Patent Archer, Charles J [Rochester, MN]; Blocksome, Michael A [Rochester, MN]

Methods, systems, and products are disclosed for chaining DMA data transfer operations for compute nodes in a parallel computer that include: receiving, by an origin DMA engine on an origin node in an origin injection FIFO buffer for the origin DMA engine, a RGET data descriptor specifying a DMA transfer operation data descriptor on the origin node and a second RGET data descriptor on the origin node, the second RGET data descriptor specifying a target RGET data descriptor on the target node, the target RGET data descriptor specifying an additional DMA transfer operation data descriptor on the origin node; creating,more » « less
Full Text Available
Self-pacing direct memory access data transfer operations for compute nodes in a parallel computer

Patent Blocksome, Michael A

Methods, apparatus, and products are disclosed for self-pacing DMA data transfer operations for nodes in a parallel computer that include: transferring, by an origin DMA on an origin node, a RTS message to a target node, the RTS message specifying an message on the origin node for transfer to the target node; receiving, in an origin injection FIFO for the origin DMA from a target DMA on the target node in response to transferring the RTS message, a target RGET descriptor followed by a DMA transfer operation descriptor, the DMA descriptor for transmitting a message portion to the target node,more » « less
Full Text Available

Similar Records

Title: Thermal aware data placement and compute dispatch in a memory system

Abstract

Citation Formats

Hybrid drive migrating high workload data from disk to non-volatile semiconductor memory patent, February 2016

Thermally-Aware Process Scheduling patent-application, August 2015

Methods and apparatuses for heat management in information systems patent-application, March 2009

Storage System, Storage Apparatus, Control Methods of Storage System, and Computer Product patent-application, October 2014

Dynamic Management of Thermal Loads patent-application, November 2013

TOP-PIM: throughput-oriented programmable processing in memory conference, January 2014

Memory Storage Device, Memory Controller, and Temperature Management Method patent-application, March 2013

Hybrid Storage Aggregate Block Tracking patent-application, September 2013

Systems and Methods for Memory System Management Based on Thermal Information of a Memory System patent-application, September 2014

Integrated calibration apparatus for a multi-mode information storage system patent, November 1999

Storage Device and Global Garbage Collection Method of Data Storage System Including the Same patent-application, December 2014

Data Storage Device patent-application, September 2009

Disk drive that positions a head at multiple head-to-disk spacings patent, January 2008

Disc drive apparatus patent-application, May 2006

Power Control in a Dispersed Storage Network patent-application, October 2014

Variable refresh control for a memory patent, August 2004

Memory device and method of accessing a memory device patent, October 2004

Storage system and storage control method achieving both power saving and good performance patent-application, December 2007

Transparent continuous refresh RAM cell architecture patent, August 2002

Maintaining level heat emission in multiprocessor by rectifying dispatch table assigned with static tasks scheduling using assigned task parameters patent, January 2011

A survey of architectural techniques for DRAM power management journal, January 2012

Arrayed processing element redundancy architecture patent-application, September 2003

System-on-chip with memory speed control core patent, May 2013

Dynamic Operations for 3D Stacked Memory Using Thermal Data patent-application, October 2013

Thermal modeling and management of DRAM memory systems conference, January 2007

Interface for solid-state memory patent, April 2012

Dynamic Storage Based on Performance Throttling patent-application, October 2008

Non-volatile storage subsystem with energy-based performance throttling patent, July 2014

Storage Device patent-application, November 2011

Method and system for utilizing DRAM components in a system-on-chip patent-application, June 2008

Method and apparatus for using smart memories in computing patent-application, January 2003

Memory Subsystem and Computer System patent-application, January 2014

Memory System Connector patent-application, April 2014

Multi-Level Memory Architecture With Data Prioritization patent-application, January 2008

Non-volatile memory management patent-application, August 2007

Apparatus, System and Method for Managing Lifetime of a Storage Device patent-application, March 2012

Memory Data Management patent-application, December 2014

Controlling Sprinting for Thermal Capacity Boosted Systems patent-application, December 2014

Memory access system, address converter, and address conversion method capable of reducing a memory access time patent, March 2002

Online Data Movement Without Compromising Data Integrity patent-application, March 2016

Method for adaptive formatting and track traversal in data storage devices patent, October 2000

System and method for adaptively configuring an L2 cache memory mesh patent, April 2014

System and method for selective memory module power management patent, September 2008

Dynamic DASD data management and partitioning based on access frequency utilization and capacity patent, November 2001

Disk Drive With Multiple Level Power Reduction During Write patent-application, December 2008

Logical disk management method and apparatus patent-application, January 2006

A comprehensive study of energy efficiency and performance of flash-based SSD journal, April 2011

System and Method for Controlling Various Aspects of PCIe Direct Attached Nonvolatile Memory Storage Subsystems patent-application, March 2016

System, Method and Computer Program Product for Multi-Thread Operation Involving First Memory of a First Memory Class and Second Memory of a Second Memory Class patent-application, May 2015

Dynamic updating of thresholds in accordance with operating conditons patent-application, July 2010

Memory Circuitry Including Computational Circuity for Performing Supplemental Functions patent-application, July 2014

Thermally Sensitive Wear Leveling for a Flash Memory Device that Includes a Plurality of Flash Memory Modules patent-application, March 2016

Apparatus and method for a memory unit with a processor integrated therein patent, October 1997

Information Processing Apparatus, Control Method Therefor, and Computer-Readable Storage Medium patent-application, June 2014

Hybrid Storage Device and Method of Operating the Same patent-application, June 2013

Access controller for storage devices patent-application, April 2005

Multiple class memory systems patent, January 2015

Hybrid drive migrating high workload data from disk to non-volatile semiconductor memory
patent, February 2016

Thermally-Aware Process Scheduling
patent-application, August 2015

Methods and apparatuses for heat management in information systems
patent-application, March 2009

Storage System, Storage Apparatus, Control Methods of Storage System, and Computer Product
patent-application, October 2014

Dynamic Management of Thermal Loads
patent-application, November 2013

TOP-PIM: throughput-oriented programmable processing in memory
conference, January 2014

Memory Storage Device, Memory Controller, and Temperature Management Method
patent-application, March 2013

Hybrid Storage Aggregate Block Tracking
patent-application, September 2013

Systems and Methods for Memory System Management Based on Thermal Information of a Memory System
patent-application, September 2014

Integrated calibration apparatus for a multi-mode information storage system
patent, November 1999

Storage Device and Global Garbage Collection Method of Data Storage System Including the Same
patent-application, December 2014

Data Storage Device
patent-application, September 2009

Disk drive that positions a head at multiple head-to-disk spacings
patent, January 2008

Disc drive apparatus
patent-application, May 2006

Power Control in a Dispersed Storage Network
patent-application, October 2014

Variable refresh control for a memory
patent, August 2004

Memory device and method of accessing a memory device
patent, October 2004

Storage system and storage control method achieving both power saving and good performance
patent-application, December 2007

Transparent continuous refresh RAM cell architecture
patent, August 2002

Maintaining level heat emission in multiprocessor by rectifying dispatch table assigned with static tasks scheduling using assigned task parameters
patent, January 2011

A survey of architectural techniques for DRAM power management
journal, January 2012

Arrayed processing element redundancy architecture
patent-application, September 2003

System-on-chip with memory speed control core
patent, May 2013

Dynamic Operations for 3D Stacked Memory Using Thermal Data
patent-application, October 2013

Thermal modeling and management of DRAM memory systems
conference, January 2007

Interface for solid-state memory
patent, April 2012

Dynamic Storage Based on Performance Throttling
patent-application, October 2008

Non-volatile storage subsystem with energy-based performance throttling
patent, July 2014

Storage Device
patent-application, November 2011

Method and system for utilizing DRAM components in a system-on-chip
patent-application, June 2008

Method and apparatus for using smart memories in computing
patent-application, January 2003

Memory Subsystem and Computer System
patent-application, January 2014

Memory System Connector
patent-application, April 2014

Multi-Level Memory Architecture With Data Prioritization
patent-application, January 2008

Non-volatile memory management
patent-application, August 2007

Apparatus, System and Method for Managing Lifetime of a Storage Device
patent-application, March 2012

Memory Data Management
patent-application, December 2014

Controlling Sprinting for Thermal Capacity Boosted Systems
patent-application, December 2014

Memory access system, address converter, and address conversion method capable of reducing a memory access time
patent, March 2002

Online Data Movement Without Compromising Data Integrity
patent-application, March 2016

Method for adaptive formatting and track traversal in data storage devices
patent, October 2000

System and method for adaptively configuring an L2 cache memory mesh
patent, April 2014

System and method for selective memory module power management
patent, September 2008

Dynamic DASD data management and partitioning based on access frequency utilization and capacity
patent, November 2001

Disk Drive With Multiple Level Power Reduction During Write
patent-application, December 2008

Logical disk management method and apparatus
patent-application, January 2006

A comprehensive study of energy efficiency and performance of flash-based SSD
journal, April 2011

System and Method for Controlling Various Aspects of PCIe Direct Attached Nonvolatile Memory Storage Subsystems
patent-application, March 2016

System, Method and Computer Program Product for Multi-Thread Operation Involving First Memory of a First Memory Class and Second Memory of a Second Memory Class
patent-application, May 2015

Dynamic updating of thresholds in accordance with operating conditons
patent-application, July 2010

Memory Circuitry Including Computational Circuity for Performing Supplemental Functions
patent-application, July 2014

Thermally Sensitive Wear Leveling for a Flash Memory Device that Includes a Plurality of Flash Memory Modules
patent-application, March 2016

Apparatus and method for a memory unit with a processor integrated therein
patent, October 1997

Information Processing Apparatus, Control Method Therefor, and Computer-Readable Storage Medium
patent-application, June 2014

Hybrid Storage Device and Method of Operating the Same
patent-application, June 2013

Access controller for storage devices
patent-application, April 2005

Multiple class memory systems
patent, January 2015