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Title: Thermal aware data placement and compute dispatch in a memory system

Abstract

A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.

Inventors:
; ; ; ;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1532082
Patent Number(s):
9,947,386
Application Number:
14/492,045
Assignee:
Advanced Micro Devices, Inc. (Sunnyvale, CA)
DOE Contract Number:  
AC52-07NA27344; B600716
Resource Type:
Patent
Resource Relation:
Patent File Date: 2014-09-21
Country of Publication:
United States
Language:
English

Citation Formats

Arora, Manish, Paul, Indrani, Eckert, Yasuko, Jayasena, Nuwan, and Zhang, Dong Ping. Thermal aware data placement and compute dispatch in a memory system. United States: N. p., 2018. Web.
Arora, Manish, Paul, Indrani, Eckert, Yasuko, Jayasena, Nuwan, & Zhang, Dong Ping. Thermal aware data placement and compute dispatch in a memory system. United States.
Arora, Manish, Paul, Indrani, Eckert, Yasuko, Jayasena, Nuwan, and Zhang, Dong Ping. Tue . "Thermal aware data placement and compute dispatch in a memory system". United States. https://www.osti.gov/servlets/purl/1532082.
@article{osti_1532082,
title = {Thermal aware data placement and compute dispatch in a memory system},
author = {Arora, Manish and Paul, Indrani and Eckert, Yasuko and Jayasena, Nuwan and Zhang, Dong Ping},
abstractNote = {A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {4}
}

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