Title: Thermal aware data placement and compute dispatch in a memory system

Abstract

A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.

Inventors:

Arora, Manish; Paul, Indrani; Eckert, Yasuko; Jayasena, Nuwan; Zhang, Dong Ping

Issue Date:

2018-04-17

Research Org.:

Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1532082

Patent Number(s):

9947386

Application Number:

14/492,045

Assignee:

Advanced Micro Devices, Inc. (Sunnyvale, CA)

Patent Classifications (CPCs):

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES

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G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES

G11C11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
G11C5/025 - {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
G11C7/04 - with means for avoiding disturbances due to temperature effects
G11C8/12 - Group selection circuits, e.g. for memory block selections, chip selection, array selection

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DOE Contract Number:  

AC52-07NA27344; B600716

Resource Type:

Patent

Resource Relation:

Patent File Date: 2014-09-21

Country of Publication:

United States

Language:

English