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Title: Pausible bisynchronous FIFO

Abstract

A system, method, and computer program product are provided for a pausible bisynchronous FIFO. Data is written synchronously with a first clock signal of a first clock domain to an entry of a dual-port memory array and an increment signal is generated in the first clock domain. The increment signal is determined to transition near an edge of a second dock signal, where the second clock signal is a pausible clock signal. A next edge of the second clock signal of the second clock domain is delayed and the increment signal to the second clock domain and is transmitted.

Inventors:
; ;
Issue Date:
Research Org.:
NVIDIA Corp., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1531995
Patent Number(s):
9,672,008
Application Number:
14/948,175
Assignee:
NVIDIA Corporation (Santa Clara, CA)
DOE Contract Number:  
B599861
Resource Type:
Patent
Resource Relation:
Patent File Date: 2015-11-20
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Keller, Benjamin Andrew, Fojtik, Matthew Rudolph, and Khailany, Brucek Kurdo. Pausible bisynchronous FIFO. United States: N. p., 2017. Web.
Keller, Benjamin Andrew, Fojtik, Matthew Rudolph, & Khailany, Brucek Kurdo. Pausible bisynchronous FIFO. United States.
Keller, Benjamin Andrew, Fojtik, Matthew Rudolph, and Khailany, Brucek Kurdo. Tue . "Pausible bisynchronous FIFO". United States. https://www.osti.gov/servlets/purl/1531995.
@article{osti_1531995,
title = {Pausible bisynchronous FIFO},
author = {Keller, Benjamin Andrew and Fojtik, Matthew Rudolph and Khailany, Brucek Kurdo},
abstractNote = {A system, method, and computer program product are provided for a pausible bisynchronous FIFO. Data is written synchronously with a first clock signal of a first clock domain to an entry of a dual-port memory array and an increment signal is generated in the first clock domain. The increment signal is determined to transition near an edge of a second dock signal, where the second clock signal is a pausible clock signal. A next edge of the second clock signal of the second clock domain is delayed and the increment signal to the second clock domain and is transmitted.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2017},
month = {6}
}

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Works referenced in this record:

Low latency FIFO circuits for mixed asynchronous and synchronous systems
patent, February 2005


Method and apparatus for synchronizing parallel data transfer
patent, April 1997