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Title: Technique for grouping instructions into independent strands

Abstract

A device compiler and linker is configured to group instructions into different strands for execution by different threads based on the dependence of those instructions on other, long-latency instructions. A thread may execute a strand that includes long-latency instructions, and then hardware resources previously allocated for the execution of that thread may be de-allocated from the thread and re-allocated to another thread. The other thread may then execute another strand while the long-latency instructions are in flight. With this approach, the other thread is not required to wait for the long-latency instructions to complete before acquiring hardware resources and initiating execution of the other strand, thereby eliminating at least a portion of the time that the other thread would otherwise spend waiting.

Inventors:
; ;
Issue Date:
Research Org.:
NVIDIA Corp., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1531988
Patent Number(s):
9,645,802
Application Number:
13/961,097
Assignee:
NVIDIA Corporation (Santa Clara, CA)
DOE Contract Number:  
B599861; HR0011-13-3-0001
Resource Type:
Patent
Resource Relation:
Patent File Date: 2013-08-07
Country of Publication:
United States
Language:
English

Citation Formats

Mehrara, Mojtaba, Garland, Michael, and Diamos, Gregory. Technique for grouping instructions into independent strands. United States: N. p., 2017. Web.
Mehrara, Mojtaba, Garland, Michael, & Diamos, Gregory. Technique for grouping instructions into independent strands. United States.
Mehrara, Mojtaba, Garland, Michael, and Diamos, Gregory. Tue . "Technique for grouping instructions into independent strands". United States. https://www.osti.gov/servlets/purl/1531988.
@article{osti_1531988,
title = {Technique for grouping instructions into independent strands},
author = {Mehrara, Mojtaba and Garland, Michael and Diamos, Gregory},
abstractNote = {A device compiler and linker is configured to group instructions into different strands for execution by different threads based on the dependence of those instructions on other, long-latency instructions. A thread may execute a strand that includes long-latency instructions, and then hardware resources previously allocated for the execution of that thread may be de-allocated from the thread and re-allocated to another thread. The other thread may then execute another strand while the long-latency instructions are in flight. With this approach, the other thread is not required to wait for the long-latency instructions to complete before acquiring hardware resources and initiating execution of the other strand, thereby eliminating at least a portion of the time that the other thread would otherwise spend waiting.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2017},
month = {5}
}

Patent:

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