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Title: Transistor with elevated drain termination

Abstract

According to an exemplary implementation, a transistor includes drain finger electrodes interdigitated with source finger electrodes. The transistor also includes a current conduction path in a semiconductor substrate between the drain finger electrodes and the source finger electrodes. At least one of the drain finger electrodes has a drain finger electrode end and a drain finger electrode main body, where the drain finger electrode main body is non-coplaner with at least a portion of the drain finger electrode end. The transistor may also include a dielectric material situated between at least a portion of the drain finger electrode end and the semiconductor substrate. The dielectric material can be an increasing thickness dielectric material. The dielectric material can thus elevate the drain finger electrode end over the semiconductor substrate. Further, the drain finger electrode end can have an increased radius of curvature.

Inventors:
;
Issue Date:
Research Org.:
Infineon Technologies Americas Corp., El Segundo, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1531972
Patent Number(s):
9564498
Application Number:
14/750,262
Assignee:
Infineon Technologies Americas Corp. (El Segundo, CA)
Patent Classifications (CPCs):
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
DOE Contract Number:  
AR0000016
Resource Type:
Patent
Resource Relation:
Patent File Date: 2015-06-25
Country of Publication:
United States
Language:
English

Citation Formats

Briere, Michael A., and Garg, Reenu. Transistor with elevated drain termination. United States: N. p., 2017. Web.
Briere, Michael A., & Garg, Reenu. Transistor with elevated drain termination. United States.
Briere, Michael A., and Garg, Reenu. Tue . "Transistor with elevated drain termination". United States. https://www.osti.gov/servlets/purl/1531972.
@article{osti_1531972,
title = {Transistor with elevated drain termination},
author = {Briere, Michael A. and Garg, Reenu},
abstractNote = {According to an exemplary implementation, a transistor includes drain finger electrodes interdigitated with source finger electrodes. The transistor also includes a current conduction path in a semiconductor substrate between the drain finger electrodes and the source finger electrodes. At least one of the drain finger electrodes has a drain finger electrode end and a drain finger electrode main body, where the drain finger electrode main body is non-coplaner with at least a portion of the drain finger electrode end. The transistor may also include a dielectric material situated between at least a portion of the drain finger electrode end and the semiconductor substrate. The dielectric material can be an increasing thickness dielectric material. The dielectric material can thus elevate the drain finger electrode end over the semiconductor substrate. Further, the drain finger electrode end can have an increased radius of curvature.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Feb 07 00:00:00 EST 2017},
month = {Tue Feb 07 00:00:00 EST 2017}
}

Works referenced in this record:

High voltage MIS field effect transistor
patent, June 1996


Structure and Layout of a FET Prime Cell
patent-application, April 2006


LDMOS transistor with enhanced termination region for high breakdown voltage with low on-resistance
patent-application, September 2004