skip to main content
DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: System and method for hardware scheduling of conditional barriers and impatient barriers

Abstract

A method and a system are provided for hardware scheduling of barrier instructions. Execution of a plurality of threads to process instructions of a program that includes a barrier instruction is initiated, and when each thread reaches the barrier instruction during execution of program, it is determined whether the thread participates in the barrier instruction. The threads that participate in the barrier instruction are then serially executed to process one or more instructions of the program that follow the barrier instruction. A method and system are also provided for impatient scheduling of barrier instructions. When a portion of the threads that is greater than a minimum number of threads and less than all of the threads in the plurality of threads reaches the barrier instruction each of the threads in the portion is serially executed to process one or more instructions of the program that follow the barrier instruction.

Inventors:
; ; ;
Issue Date:
Research Org.:
NVIDIA Corp. Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1531944
Patent Number(s):
9448803
Application Number:
13/794,578
Assignee:
NVIDIA Corporation (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
B599861
Resource Type:
Patent
Resource Relation:
Patent File Date: 2013-03-11
Country of Publication:
United States
Language:
English

Citation Formats

Lindholm, John Erik, Karras, Tero Tapani, Aila, Timo Oskari, and Laine, Samuli Matias. System and method for hardware scheduling of conditional barriers and impatient barriers. United States: N. p., 2016. Web.
Lindholm, John Erik, Karras, Tero Tapani, Aila, Timo Oskari, & Laine, Samuli Matias. System and method for hardware scheduling of conditional barriers and impatient barriers. United States.
Lindholm, John Erik, Karras, Tero Tapani, Aila, Timo Oskari, and Laine, Samuli Matias. Tue . "System and method for hardware scheduling of conditional barriers and impatient barriers". United States. https://www.osti.gov/servlets/purl/1531944.
@article{osti_1531944,
title = {System and method for hardware scheduling of conditional barriers and impatient barriers},
author = {Lindholm, John Erik and Karras, Tero Tapani and Aila, Timo Oskari and Laine, Samuli Matias},
abstractNote = {A method and a system are provided for hardware scheduling of barrier instructions. Execution of a plurality of threads to process instructions of a program that includes a barrier instruction is initiated, and when each thread reaches the barrier instruction during execution of program, it is determined whether the thread participates in the barrier instruction. The threads that participate in the barrier instruction are then serially executed to process one or more instructions of the program that follow the barrier instruction. A method and system are also provided for impatient scheduling of barrier instructions. When a portion of the threads that is greater than a minimum number of threads and less than all of the threads in the plurality of threads reaches the barrier instruction each of the threads in the portion is serially executed to process one or more instructions of the program that follow the barrier instruction.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2016},
month = {9}
}

Patent:

Save / Share:

Works referenced in this record:

Virtual multithreading translation mechanism including retrofit capability
patent, February 2010


Program thread syncronization
patent-application, May 2007