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Title: System and method for hardware scheduling of indexed barriers

Abstract

A method and a system are provided for hardware scheduling of indexed barrier instructions. Execution of a plurality of threads to process instructions of a program that includes a barrier instruction is initiated and when each thread reaches the barrier instruction, the thread pauses execution of the instructions. A first sub-group of threads in the plurality of threads is associated with a first sub-barrier index and a second sub-group of threads in the plurality of threads is associated with a second sub-barrier index. When the barrier instruction can be scheduled for execution, threads in the first sub-group are executed serially and threads in the second sub-group are executed serially and at least one thread in the first sub-group is executed in parallel with at least one thread in the second sub-group.

Inventors:
;
Issue Date:
Research Org.:
NVIDIA Corp., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1531942
Patent Number(s):
9442755
Application Number:
13/844,541
Assignee:
NVIDIA Corporation (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
B599861
Resource Type:
Patent
Resource Relation:
Patent File Date: 2013-03-15
Country of Publication:
United States
Language:
English

Citation Formats

Lindholm, John Erik, and Karras, Tero Tapani. System and method for hardware scheduling of indexed barriers. United States: N. p., 2016. Web.
Lindholm, John Erik, & Karras, Tero Tapani. System and method for hardware scheduling of indexed barriers. United States.
Lindholm, John Erik, and Karras, Tero Tapani. Tue . "System and method for hardware scheduling of indexed barriers". United States. https://www.osti.gov/servlets/purl/1531942.
@article{osti_1531942,
title = {System and method for hardware scheduling of indexed barriers},
author = {Lindholm, John Erik and Karras, Tero Tapani},
abstractNote = {A method and a system are provided for hardware scheduling of indexed barrier instructions. Execution of a plurality of threads to process instructions of a program that includes a barrier instruction is initiated and when each thread reaches the barrier instruction, the thread pauses execution of the instructions. A first sub-group of threads in the plurality of threads is associated with a first sub-barrier index and a second sub-group of threads in the plurality of threads is associated with a second sub-barrier index. When the barrier instruction can be scheduled for execution, threads in the first sub-group are executed serially and threads in the second sub-group are executed serially and at least one thread in the first sub-group is executed in parallel with at least one thread in the second sub-group.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2016},
month = {9}
}

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Works referenced in this record:

Virtual multithreading translation mechanism including retrofit capability
patent, February 2010


Program thread syncronization
patent-application, May 2007