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Title: Sense amplifier with transistor threshold compensation

Abstract

One embodiment provides, in a sense amplifier for an electronic memory array in which a selected memory cell drives a developing voltage differential according to a logic state of the memory cell, a method to store the logic state. The method includes poising source voltages of first and second transistors at levels offset, respectively, by threshold voltages of the first and second transistors. The method also includes applying the voltage differential between a gate of the first transistor and a gate of the second transistor, the first and second transistors configured to oppose each other in a cross-coupled inverter stage of the sense amplifier.

Inventors:
;
Issue Date:
Research Org.:
NVIDIA Corp., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1531930
Patent Number(s):
9,418,714
Application Number:
13/941,151
Assignee:
NVIDIA Corporation (Santa Clara, CA)
DOE Contract Number:  
B599861; HR0011-13-3-0001
Resource Type:
Patent
Resource Relation:
Patent File Date: 2013-07-12
Country of Publication:
United States
Language:
English

Citation Formats

Sinangil, Mahmut E., and Poulton, John W. Sense amplifier with transistor threshold compensation. United States: N. p., 2016. Web.
Sinangil, Mahmut E., & Poulton, John W. Sense amplifier with transistor threshold compensation. United States.
Sinangil, Mahmut E., and Poulton, John W. Tue . "Sense amplifier with transistor threshold compensation". United States. https://www.osti.gov/servlets/purl/1531930.
@article{osti_1531930,
title = {Sense amplifier with transistor threshold compensation},
author = {Sinangil, Mahmut E. and Poulton, John W.},
abstractNote = {One embodiment provides, in a sense amplifier for an electronic memory array in which a selected memory cell drives a developing voltage differential according to a logic state of the memory cell, a method to store the logic state. The method includes poising source voltages of first and second transistors at levels offset, respectively, by threshold voltages of the first and second transistors. The method also includes applying the voltage differential between a gate of the first transistor and a gate of the second transistor, the first and second transistors configured to oppose each other in a cross-coupled inverter stage of the sense amplifier.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2016},
month = {8}
}

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Works referenced in this record:

Address multiplexing in pseudo-dual port memory
patent, October 2013


Differential correlated double sampling DRAM sense amplifier
patent, October 2001


Latch with a feedback circuit
patent, June 2014


Static memory having self-timing circuit
patent, November 2003


Content addressable memory
patent, April 2012