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Title: Partitionable memory interfaces

Abstract

A memory device receives a plurality of read commands and/or write commands in parallel. The memory device transmits data corresponding to respective read commands on respective portions of a data bus and receives data corresponding to respective write commands on respective portions of the data bus. The memory device includes I/O logic to receive the plurality of read commands in parallel, to transmit the data corresponding to the respective read commands on respective portions of the data bus, and to receive the data corresponding to the respective write commands on respective portions of the data bus.

Inventors:
Issue Date:
Research Org.:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1531929
Patent Number(s):
9417816
Application Number:
14/146,618
Assignee:
Advanced Micro Devices, Inc. (Sunnyvale, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
DOE Contract Number:  
AC52-07NA27344; B600716
Resource Type:
Patent
Resource Relation:
Patent File Date: 2014-01-02
Country of Publication:
United States
Language:
English

Citation Formats

Roberts, David A. Partitionable memory interfaces. United States: N. p., 2016. Web.
Roberts, David A. Partitionable memory interfaces. United States.
Roberts, David A. Tue . "Partitionable memory interfaces". United States. https://www.osti.gov/servlets/purl/1531929.
@article{osti_1531929,
title = {Partitionable memory interfaces},
author = {Roberts, David A.},
abstractNote = {A memory device receives a plurality of read commands and/or write commands in parallel. The memory device transmits data corresponding to respective read commands on respective portions of a data bus and receives data corresponding to respective write commands on respective portions of the data bus. The memory device includes I/O logic to receive the plurality of read commands in parallel, to transmit the data corresponding to the respective read commands on respective portions of the data bus, and to receive the data corresponding to the respective write commands on respective portions of the data bus.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2016},
month = {8}
}

Works referenced in this record:

Configurable Memory Device
patent-application, October 2011


Pseudo Dual-Ported SRAM
patent-application, June 2010


Data Handling System Comprising a Rearrangement Network
patent-application, March 2011


Address generator with controllable modulo power of two addressing capability
patent, February 1997


Tracking deferred data transfers on a system-interconnect bus
patent-application, June 2003


Method and apparatus for formatting vital component data in a field replaceable unit of a computer system
patent-application, August 2004


Test algorithm selection in memory built-in self test controller
patent-application, August 2007


Adaptive bus profiler
patent, May 2011


    Works referencing / citing this record:

    Memory access techniques in memory devices with multiple partitions
    patent, December 2018