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Title: Math processing by detection of elementary valued operands

Abstract

One embodiment of the present invention includes a method for simplifying arithmetic operations by detecting operands with elementary values such as zero or 1.0. Computer and graphics processing systems perform a great number of multiply-add operations. In a significant portion of these operations, the values of one or more of the operands are zero or 1.0. By detecting the occurrence of these elementary values, math operations can be greatly simplified, for example by eliminating multiply operations when one multiplicand is zero or 1.0 or eliminating add operations when one addend is zero. The simplified math operations resulting from detecting elementary valued operands provide significant savings in overhead power, dynamic processing power, and cycle time.

Inventors:
; ;
Issue Date:
Research Org.:
NVIDIA Corp., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1531918
Patent Number(s):
9383968
Application Number:
14/040,370
Assignee:
NVIDIA Corporation (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
B599861
Resource Type:
Patent
Resource Relation:
Patent File Date: 2013-09-27
Country of Publication:
United States
Language:
English

Citation Formats

Finchelstein, Daniel Frederic, Tannenbaum, David, and Iyer, Srinivasan Vasu. Math processing by detection of elementary valued operands. United States: N. p., 2016. Web.
Finchelstein, Daniel Frederic, Tannenbaum, David, & Iyer, Srinivasan Vasu. Math processing by detection of elementary valued operands. United States.
Finchelstein, Daniel Frederic, Tannenbaum, David, and Iyer, Srinivasan Vasu. Tue . "Math processing by detection of elementary valued operands". United States. https://www.osti.gov/servlets/purl/1531918.
@article{osti_1531918,
title = {Math processing by detection of elementary valued operands},
author = {Finchelstein, Daniel Frederic and Tannenbaum, David and Iyer, Srinivasan Vasu},
abstractNote = {One embodiment of the present invention includes a method for simplifying arithmetic operations by detecting operands with elementary values such as zero or 1.0. Computer and graphics processing systems perform a great number of multiply-add operations. In a significant portion of these operations, the values of one or more of the operands are zero or 1.0. By detecting the occurrence of these elementary values, math operations can be greatly simplified, for example by eliminating multiply operations when one multiplicand is zero or 1.0 or eliminating add operations when one addend is zero. The simplified math operations resulting from detecting elementary valued operands provide significant savings in overhead power, dynamic processing power, and cycle time.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2016},
month = {7}
}

Works referenced in this record:

Method and apparatus for parallel arithmetic operations
patent, September 2009


Power saving in a floating point unit using a multiplier and aligner bypass
patent, June 2006