Title: Ground-referenced single-ended signaling connected graphics processing unit multi-chip module

Abstract

A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Inventors:

Dally, William J.; Alben, Jonah M.; Poulton, John W.; Greer, III, Thomas Hastings

Issue Date:

Tue Oct 06 00:00:00 EDT 2015

Research Org.:

NVIDIA Corp., Santa Clara, CA (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1531817

Patent Number(s):

9153539

Application Number:

13/973,947

Assignee:

NVIDIA Corporation (Santa Clara, CA)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F13/4072 - {Drivers or receivers

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

H01L2224/16145 - the bodies being stacked
H01L2224/16225 - the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L23/535 - including internal interconnections, e.g. cross-under constructions {
H01L2924/00 - Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L2924/13091 - Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
H01L2924/15192 - Resurf arrangement of the internal vias
H01L2924/15311 - being a ball array, e.g. BGA

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE

H03K19/00 - Logic circuits, i.e. having at least two inputs acting on one output

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

Y02D10/00 - Energy efficient computing

Show less

DOE Contract Number:  

B599861

Resource Type:

Patent

Resource Relation:

Patent File Date: 2013-08-22

Country of Publication:

United States

Language:

English