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Title: Ground-referenced single-ended memory interconnect

Abstract

A system is provided for transmitting signals. The system includes a ground-referenced single-ended signaling (GRS) driver circuit that is configured to pre-charge a first capacitor to store a first charge between a first output node and a first reference node based on a first input data signal during a first pre-charge phase and drive an output signal relative to a ground network based on the first charge during a first drive phase. A control circuit is configured to generate a first set of control signals based on the first input data signal and a first clock signal, where the first set of control signals causes the first GRS driver circuit to operate in either the first pre-charge phase or in the first drive phase.

Inventors:
Issue Date:
Research Org.:
NVIDIA Corp., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1531816
Patent Number(s):
9153314
Application Number:
13/890,899
Assignee:
NVIDIA Corporation (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
DOE Contract Number:  
B599861
Resource Type:
Patent
Resource Relation:
Patent File Date: 2013-05-09
Country of Publication:
United States
Language:
English

Citation Formats

Dally, William J. Ground-referenced single-ended memory interconnect. United States: N. p., 2015. Web.
Dally, William J. Ground-referenced single-ended memory interconnect. United States.
Dally, William J. Tue . "Ground-referenced single-ended memory interconnect". United States. https://www.osti.gov/servlets/purl/1531816.
@article{osti_1531816,
title = {Ground-referenced single-ended memory interconnect},
author = {Dally, William J.},
abstractNote = {A system is provided for transmitting signals. The system includes a ground-referenced single-ended signaling (GRS) driver circuit that is configured to pre-charge a first capacitor to store a first charge between a first output node and a first reference node based on a first input data signal during a first pre-charge phase and drive an output signal relative to a ground network based on the first charge during a first drive phase. A control circuit is configured to generate a first set of control signals based on the first input data signal and a first clock signal, where the first set of control signals causes the first GRS driver circuit to operate in either the first pre-charge phase or in the first drive phase.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2015},
month = {10}
}

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Works referenced in this record:

Regulated inverting power supply
patent, September 2000


Ground Referenced Single-Ended Signaling
patent-application, February 2014


Charge domain filter and method thereof
patent, April 2014


Semiconductor chip and multi-chip package
patent, August 2010


On-package multiprocessor ground-referenced single-ended interconnect
patent, October 2014


Ground referenced single-ended signaling
patent, December 2013


Circuit with programmable signal bandwidth and method thereof
patent, June 2011


Incorporating an independent logic block in a system-on-a-chip
patent, March 2013


Multi-chip build-up package of optoelectronic chip
patent, October 2008


Uniform multi-chip identification and routing system
patent, December 2013


Ground-Referenced Single-Ended Memory Interconnect
patent-application, September 2014


Systems and methods for control with a multi-chip module with multiple dies
patent, September 2013


    Works referencing / citing this record:

    Data-driven charge-pump transmitter for differential signaling
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