System and method for configuring a channel

Keckler, Stephen William; Dally, William J.; Scott, Steven Lee; Khailany, Brucek Kurdo; Parker, Michael Allen

Title: System and method for configuring a channel

Abstract

A system and method are provided for configuring a plurality of pin resources. The method includes identifying a plurality of pin resources of a primary application specific integrated circuit (ASIC) device and configuring the plurality of pin resources based on a pin distribution between a first interface and a second interface, where the first interface provides a first communication path between the primary ASIC device and a first device, and the second interface provides a second communication path between the primary ASIC device and a second device.

Inventors:: Keckler, Stephen William; Dally, William J.; Scott, Steven Lee; Khailany, Brucek Kurdo; Parker, Michael Allen

Issue Date:: 2015-06-16

Research Org.:: NVIDIA Corp., Santa Clara, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1531805

Patent Number(s):: 9058453

Application Number:: 13/902,701

Assignee:: NVIDIA Corporation (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F13/1668 - {Details of memory controller}
G06F13/4068 - {Electrical coupling}
G06F13/409 - {Mechanical coupling
G06F30/34 - for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

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DOE Contract Number:: B599861

Resource Type:: Patent

Resource Relation:: Patent File Date: 2013-05-24

Country of Publication:: United States

Language:: English

Citation Formats


                    Keckler, Stephen William, Dally, William J., Scott, Steven Lee, Khailany, Brucek Kurdo, and Parker, Michael Allen. System and method for configuring a channel.  United States: N. p., 2015. 
        Web.

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                    Keckler, Stephen William, Dally, William J., Scott, Steven Lee, Khailany, Brucek Kurdo, & Parker, Michael Allen. System and method for configuring a channel.  United States.

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                    Keckler, Stephen William, Dally, William J., Scott, Steven Lee, Khailany, Brucek Kurdo, and Parker, Michael Allen. Tue .  
        "System and method for configuring a channel".  United States.  https://www.osti.gov/servlets/purl/1531805.

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@article{osti_1531805,

  title        = {System and method for configuring a channel},

  author       = {Keckler, Stephen William and Dally, William J. and Scott, Steven Lee and Khailany, Brucek Kurdo and Parker, Michael Allen},

  abstractNote = {A system and method are provided for configuring a plurality of pin resources. The method includes identifying a plurality of pin resources of a primary application specific integrated circuit (ASIC) device and configuring the plurality of pin resources based on a pin distribution between a first interface and a second interface, where the first interface provides a first communication path between the primary ASIC device and a first device, and the second interface provides a second communication path between the primary ASIC device and a second device.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2015},

  month        = {6}

}

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Works referenced in this record:

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Title: System and method for configuring a channel

Abstract

Citation Formats

Method and apparatus for a pin-configurable integrated circuit tester board patent, September 1999

I/O pin placement for a programmable logic device patent, September 2006

Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool for routing patent, December 2007

Integrated circuit with configurable test pins patent, December 2012

Isolation method and package using a high isolation differential ball grid array (BGA) pattern patent, October 2013

Interactive graphical pin assignment patent, February 2014

Method and System for Pin Assignment patent-application, May 2008

Programmable system on a chip patent-application, October 2005

Timing-Optimal Placement, Pin Assignment, and Routing for Integrated Circuits patent-application, August 2010

Programmable driver for an I/O pin of an integrated circuit patent-application, September 2005

Placement of configurable input/output buffer structures during design of integrated circuits patent-application, July 2004

IC with digital and analog circuits and mixed signal I/O pins patent-application, June 2003

Method and apparatus for a pin-configurable integrated circuit tester board
patent, September 1999

I/O pin placement for a programmable logic device
patent, September 2006

Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool for routing
patent, December 2007

Integrated circuit with configurable test pins
patent, December 2012

Isolation method and package using a high isolation differential ball grid array (BGA) pattern
patent, October 2013

Interactive graphical pin assignment
patent, February 2014

Method and System for Pin Assignment
patent-application, May 2008

Programmable system on a chip
patent-application, October 2005

Timing-Optimal Placement, Pin Assignment, and Routing for Integrated Circuits
patent-application, August 2010

Programmable driver for an I/O pin of an integrated circuit
patent-application, September 2005

Placement of configurable input/output buffer structures during design of integrated circuits
patent-application, July 2004

IC with digital and analog circuits and mixed signal I/O pins
patent-application, June 2003