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Title: Low power reconfigurable circuits with delay compensation

Abstract

According to one aspect of the present disclosure, a circuit includes a semiconductor device including a plurality of logic blocks and a plurality of programmable interconnects. A delay detector generates a delay signal responsive to a measured delay of an output signal, wherein the output signal is from at least one of the plurality of logic blocks. A biasing circuit responsive to the delay signal to adjust subsequent measured delays toward a predetermined value.

Inventors:
; ; ;
Issue Date:
Research Org.:
Khatri, Sunil Papanchand, College Station, TX (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1531672
Patent Number(s):
7,880,505
Application Number:
12/709,227
Assignee:
Khatri, Sunil Papanchand, College Station, TX (United States)
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Patent
Resource Relation:
Patent File Date: 2010-02-19
Country of Publication:
United States
Language:
English

Citation Formats

Khatri, Sunil Papanchand, Vaidya, Sheila, Griffin, Timothy Kevin, and Jayakumar, Nikhil. Low power reconfigurable circuits with delay compensation. United States: N. p., 2011. Web.
Khatri, Sunil Papanchand, Vaidya, Sheila, Griffin, Timothy Kevin, & Jayakumar, Nikhil. Low power reconfigurable circuits with delay compensation. United States.
Khatri, Sunil Papanchand, Vaidya, Sheila, Griffin, Timothy Kevin, and Jayakumar, Nikhil. Tue . "Low power reconfigurable circuits with delay compensation". United States. https://www.osti.gov/servlets/purl/1531672.
@article{osti_1531672,
title = {Low power reconfigurable circuits with delay compensation},
author = {Khatri, Sunil Papanchand and Vaidya, Sheila and Griffin, Timothy Kevin and Jayakumar, Nikhil},
abstractNote = {According to one aspect of the present disclosure, a circuit includes a semiconductor device including a plurality of logic blocks and a plurality of programmable interconnects. A delay detector generates a delay signal responsive to a measured delay of an output signal, wherein the output signal is from at least one of the plurality of logic blocks. A biasing circuit responsive to the delay signal to adjust subsequent measured delays toward a predetermined value.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2011},
month = {2}
}

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Works referenced in this record:

Calibrating integrating receivers for source synchronous protocol
patent, October 2009


    Works referencing / citing this record:

    Memory with an assist determination controller and associated methods
    patent, March 2015


    Configurable delay circuitry with compensated delay
    patent, May 2014