Virtual FPGA management and optimization system

Roberts, David A.; Kegel, Andrew G.; Mednick, Elliot H.

Title: Virtual FPGA management and optimization system

Abstract

A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.

Inventors:: Roberts, David A.; Kegel, Andrew G.; Mednick, Elliot H.

Issue Date:: 2018-12-25

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1531398

Patent Number(s):: 10164639

Application Number:: 15/812,411

Assignee:: Advanced Micro Devices, Inc. (Sunnyvale, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F9/5077 - {Logical partitioning of resources
G06F15/7871 - {Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS}
G06F15/76 - Architectures of general purpose stored program computers

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
H03K19/17732 - Macroblocks
H03K19/17756 - for partial configuration or partial reconfiguration
H03K19/17728 - Reconfigurable logic blocks, e.g. lookup tables
H03K19/1776 - for memories

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F30/30 - Circuit design
G06F15/7892 - {Reconfigurable logic embedded in CPU, e.g. reconfigurable unit}
G06F15/7875 - {for multiple contexts}
G06F9/4843 - {by program, e.g. task dispatcher, supervisor, operating system}
G06F30/34 - for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F9/5011 - {the resources being hardware resources other than CPUs, Servers and Terminals}

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DOE Contract Number:: AC52-07NA27344; B620717

Resource Type:: Patent

Resource Relation:: Patent File Date: 2017-11-14

Country of Publication:: United States

Language:: English

Citation Formats


                    Roberts, David A., Kegel, Andrew G., and Mednick, Elliot H. Virtual FPGA management and optimization system.  United States: N. p., 2018. 
        Web.

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                    Roberts, David A., Kegel, Andrew G., & Mednick, Elliot H. Virtual FPGA management and optimization system.  United States.

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                    Roberts, David A., Kegel, Andrew G., and Mednick, Elliot H. Tue .  
        "Virtual FPGA management and optimization system".  United States.  https://www.osti.gov/servlets/purl/1531398.

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@article{osti_1531398,

  title        = {Virtual FPGA management and optimization system},

  author       = {Roberts, David A. and Kegel, Andrew G. and Mednick, Elliot H.},

  abstractNote = {A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2018},

  month        = {12}

}

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Works referenced in this record:

Architecture of field-programmable gate arrays
journal, July 1993

Rose, J.; El Gamal, A.; Sangiovanni-Vincentelli, A.
Proceedings of the IEEE, Vol. 81, Issue 7
https://doi.org/10.1109/5.231340

Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
patent, July 2000

New, Bernard J.; Johnson, Robert Anders; Wittig, Ralph D.
US Patent Document 6,091,263
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6091263

Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux
conference, March 2007

Rana, Vincenzo; Santambrogio, Marco; Sciuto, Donatella
2007 IEEE International Parallel and Distributed Processing Symposium
https://doi.org/10.1109/IPDPS.2007.370363

Virtualized Execution Runtime for FPGA Accelerators in the Cloud
journal, January 2017

Asiatici, Mikhail; George, Nithin; Vipin, Kizheppatt
IEEE Access, Vol. 5
https://doi.org/10.1109/ACCESS.2017.2661582

Method and apparatus for controlling a processor in a data processing system
patent, July 2007

Ryser, Peter
US Patent Document 7,243,221
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7243221

Run-time support for heterogeneous multitasking on reconfigurable SoCs
journal, October 2004

Marescaux, T.; Nollet, V.; Mignolet, J. -Y.
Integration, Vol. 38, Issue 1
https://doi.org/10.1016/j.vlsi.2004.03.002

An Enhanced Relocation Manager to Speedup Core Allocation in FPGA-based Reconfigurable Systems
conference, May 2012

Santambrogio, M. D.; Cancare, F.; Cattaneo, R.
2012 26th IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum
https://doi.org/10.1109/IPDPSW.2012.41

3D integrated circuits using thick metal for backside connections and offset bumps
patent, August 2008

Ramanathan, Shriram; Kim, Sarah E.; Morrow, Patrick R.
US Patent Document 7,410,884
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7410884

Methods and systems for assigning non-continual jobs to candidate processing nodes in a stream-oriented computer system
patent, June 2013

Bansal, Nikhil; Hildrum, Kirsten; Rajan, Deepak
US Patent Document 8,458,720
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8458720

FPGA and CPLD architectures: a tutorial
journal, July 1996

Brown, S.; Rose, J.
IEEE Design & Test of Computers, Vol. 13, Issue 2
https://doi.org/10.1109/54.500200

Network interface unit including a microcontroller having multiple configurable logic blocks, with a test/program bus for performing a plurality of selected functions
patent, May 2001

Freitag, Jr., William W.
US Patent Document 6,237,054
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6237054

Compression and decompression of configuration data using repeated data frames
patent, March 2011

Cheng, Chan-Chi Jason; Kow, San-Ta; Wu, Ann
US Patent Document 7,902,865
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7902865

Reprogrammable instruction set accelerator
patent, April 1998

Trimberger, Stephen M.
US Patent Document 5,737,631
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5737631

A VLIW processor with reconfigurable instruction set for embedded applications
journal, November 2003

Lodi, A.; Toma, M.; Campi, F.
IEEE Journal of Solid-State Circuits, Vol. 38, Issue 11
https://doi.org/10.1109/JSSC.2003.818292

Redundancy structures and methods in a programmable logic device
patent, February 2007

Chan, Michael; Leventis, Paul Mark; Lewis, David
US Patent Document 7,180,324
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7180324

Emulating power domains in an integrated circuit using partial reconfiguration
patent, January 2015

Konduru, Samskrut J.
US Patent Document 8,928,351
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8928351

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Similar Records

Title: Virtual FPGA management and optimization system

Abstract

Citation Formats

Architecture of field-programmable gate arrays journal, July 1993

Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM patent, July 2000

Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux conference, March 2007

Virtualized Execution Runtime for FPGA Accelerators in the Cloud journal, January 2017

Method and apparatus for controlling a processor in a data processing system patent, July 2007

Run-time support for heterogeneous multitasking on reconfigurable SoCs journal, October 2004

An Enhanced Relocation Manager to Speedup Core Allocation in FPGA-based Reconfigurable Systems conference, May 2012

3D integrated circuits using thick metal for backside connections and offset bumps patent, August 2008

Methods and systems for assigning non-continual jobs to candidate processing nodes in a stream-oriented computer system patent, June 2013

FPGA and CPLD architectures: a tutorial journal, July 1996

Network interface unit including a microcontroller having multiple configurable logic blocks, with a test/program bus for performing a plurality of selected functions patent, May 2001

Compression and decompression of configuration data using repeated data frames patent, March 2011

Reprogrammable instruction set accelerator patent, April 1998

A VLIW processor with reconfigurable instruction set for embedded applications journal, November 2003

Redundancy structures and methods in a programmable logic device patent, February 2007

Emulating power domains in an integrated circuit using partial reconfiguration patent, January 2015

Architecture of field-programmable gate arrays
journal, July 1993

Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
patent, July 2000

Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux
conference, March 2007

Virtualized Execution Runtime for FPGA Accelerators in the Cloud
journal, January 2017

Method and apparatus for controlling a processor in a data processing system
patent, July 2007

Run-time support for heterogeneous multitasking on reconfigurable SoCs
journal, October 2004

An Enhanced Relocation Manager to Speedup Core Allocation in FPGA-based Reconfigurable Systems
conference, May 2012

3D integrated circuits using thick metal for backside connections and offset bumps
patent, August 2008

Methods and systems for assigning non-continual jobs to candidate processing nodes in a stream-oriented computer system
patent, June 2013

FPGA and CPLD architectures: a tutorial
journal, July 1996

Network interface unit including a microcontroller having multiple configurable logic blocks, with a test/program bus for performing a plurality of selected functions
patent, May 2001

Compression and decompression of configuration data using repeated data frames
patent, March 2011

Reprogrammable instruction set accelerator
patent, April 1998

A VLIW processor with reconfigurable instruction set for embedded applications
journal, November 2003

Redundancy structures and methods in a programmable logic device
patent, February 2007

Emulating power domains in an integrated circuit using partial reconfiguration
patent, January 2015