Virtual FPGA management and optimization system

Roberts, David A.; Kegel, Andrew G.; Mednick, Elliot H.

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Title: Virtual FPGA management and optimization system

Abstract

A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.

Inventors:: Roberts, David A.; Kegel, Andrew G.; Mednick, Elliot H.

Issue Date:: 2018-12-25

Research Org.:: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1531398

Patent Number(s):: 10164639

Application Number:: 15/812,411

Assignee:: Advanced Micro Devices, Inc. (Sunnyvale, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F15/76 - Architectures of general purpose stored program computers
G06F15/7871 - {Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS}
G06F15/7875 - {for multiple contexts}
G06F15/7892 - {Reconfigurable logic embedded in CPU, e.g. reconfigurable unit}
G06F30/30 - Circuit design
G06F30/34 - for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F9/4843 - {by program, e.g. task dispatcher, supervisor, operating system}
G06F9/5011 - {the resources being hardware resources other than CPUs, Servers and Terminals}
G06F9/5077 - {Logical partitioning of resources

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
H03K19/17728 - Reconfigurable logic blocks, e.g. lookup tables
H03K19/17732 - Macroblocks
H03K19/17756 - for partial configuration or partial reconfiguration
H03K19/1776 - for memories

Show less

DOE Contract Number:: AC52-07NA27344; B620717

Resource Type:: Patent

Resource Relation:: Patent File Date: 2017-11-14

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Roberts, David A., Kegel, Andrew G., and Mednick, Elliot H. Virtual FPGA management and optimization system.  United States: N. p., 2018. 
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                    Roberts, David A., Kegel, Andrew G., & Mednick, Elliot H. Virtual FPGA management and optimization system.  United States.

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                    Roberts, David A., Kegel, Andrew G., and Mednick, Elliot H. Tue .  
        "Virtual FPGA management and optimization system".  United States.  https://www.osti.gov/servlets/purl/1531398.

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@article{osti_1531398,

  title        = {Virtual FPGA management and optimization system},

  author       = {Roberts, David A. and Kegel, Andrew G. and Mednick, Elliot H.},

  abstractNote = {A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2018},

  month        = {12}

}

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Similar Records

Title: Virtual FPGA management and optimization system

Abstract

Citation Formats

3D integrated circuits using thick metal for backside connections and offset bumps patent, August 2008

Compression and decompression of configuration data using repeated data frames patent, March 2011

Die-Stacked Memory Device with Reconfigurable Logic patent-application, June 2015

Architecture of field-programmable gate arrays journal, July 1993

Network interface unit including a microcontroller having multiple configurable logic blocks, with a test/program bus for performing a plurality of selected functions patent, May 2001

Reprogrammable instruction set accelerator patent, April 1998

Methods and systems for assigning non-continual jobs to candidate processing nodes in a stream-oriented computer system patent, June 2013

Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux conference, March 2007

Method and apparatus for controlling a processor in a data processing system patent, July 2007

Virtualized Execution Runtime for FPGA Accelerators in the Cloud journal, January 2017

Hierarchical Staging Areas for Scheduling Threads for Execution patent-application, April 2015

Run-time support for heterogeneous multitasking on reconfigurable SoCs journal, October 2004

An Enhanced Relocation Manager to Speedup Core Allocation in FPGA-based Reconfigurable Systems conference, May 2012

Emulating power domains in an integrated circuit using partial reconfiguration patent, January 2015

FPGA and CPLD architectures: a tutorial journal, July 1996

Controlling Fair Bandwidth Allocation Efficiently patent-application, July 2016

Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM patent, July 2000

A VLIW processor with reconfigurable instruction set for embedded applications journal, November 2003

Redundancy structures and methods in a programmable logic device patent, February 2007

3D integrated circuits using thick metal for backside connections and offset bumps
patent, August 2008

Compression and decompression of configuration data using repeated data frames
patent, March 2011

Die-Stacked Memory Device with Reconfigurable Logic
patent-application, June 2015

Architecture of field-programmable gate arrays
journal, July 1993

Network interface unit including a microcontroller having multiple configurable logic blocks, with a test/program bus for performing a plurality of selected functions
patent, May 2001

Reprogrammable instruction set accelerator
patent, April 1998

Methods and systems for assigning non-continual jobs to candidate processing nodes in a stream-oriented computer system
patent, June 2013

Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux
conference, March 2007

Method and apparatus for controlling a processor in a data processing system
patent, July 2007

Virtualized Execution Runtime for FPGA Accelerators in the Cloud
journal, January 2017

Hierarchical Staging Areas for Scheduling Threads for Execution
patent-application, April 2015

Run-time support for heterogeneous multitasking on reconfigurable SoCs
journal, October 2004

An Enhanced Relocation Manager to Speedup Core Allocation in FPGA-based Reconfigurable Systems
conference, May 2012

Emulating power domains in an integrated circuit using partial reconfiguration
patent, January 2015

FPGA and CPLD architectures: a tutorial
journal, July 1996

Controlling Fair Bandwidth Allocation Efficiently
patent-application, July 2016

Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
patent, July 2000

A VLIW processor with reconfigurable instruction set for embedded applications
journal, November 2003

Redundancy structures and methods in a programmable logic device
patent, February 2007