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Title: Memory synchronization filter

Abstract

Data synchronization between memories of a data processing system is achieved by transferring the data blocks from a first memory to a second memory, forming a hash list from addresses of data blocks that are written to the second memory or modified in the second memory. The hash list may be to identify a set of data blocks that are possibly written to or modified. Data blocks that are possibly modified may be written back from the second memory to the first memory in response to a synchronization event. The hash list may be updated by computing, in hardware or software, hash functions of an address of the transferred or modified data block to determine bit positions to be set. The hash list may be queried by computing hash functions of an address to determine bit positions, and checking bits in the hash list at those bit positions.

Inventors:
Issue Date:
Research Org.:
Arm Limited, Cambridge (United Kingdom)
Sponsoring Org.:
USDOE
OSTI Identifier:
1531361
Patent Number(s):
10067708
Application Number:
14/978,001
Assignee:
ARM Limited (Cambridge, GB)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
Resource Type:
Patent
Resource Relation:
Patent File Date: 2015-12-22
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Beard, Jonathan Curtis. Memory synchronization filter. United States: N. p., 2018. Web.
Beard, Jonathan Curtis. Memory synchronization filter. United States.
Beard, Jonathan Curtis. Tue . "Memory synchronization filter". United States. https://www.osti.gov/servlets/purl/1531361.
@article{osti_1531361,
title = {Memory synchronization filter},
author = {Beard, Jonathan Curtis},
abstractNote = {Data synchronization between memories of a data processing system is achieved by transferring the data blocks from a first memory to a second memory, forming a hash list from addresses of data blocks that are written to the second memory or modified in the second memory. The hash list may be to identify a set of data blocks that are possibly written to or modified. Data blocks that are possibly modified may be written back from the second memory to the first memory in response to a synchronization event. The hash list may be updated by computing, in hardware or software, hash functions of an address of the transferred or modified data block to determine bit positions to be set. The hash list may be queried by computing hash functions of an address to determine bit positions, and checking bits in the hash list at those bit positions.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {9}
}

Works referenced in this record:

In-Memory Data Rearrangement for Irregular, Data-Intensive Computing
journal, August 2015


RAIDR: Retention-aware intelligent DRAM refresh
conference, June 2012

  • Liu, Jamie; Jaiyen, Ben; Veras, Richard
  • 2012 ACM/IEEE 39th International Symposium on Computer Architecture (ISCA), 2012 39th Annual International Symposium on Computer Architecture (ISCA)
  • https://doi.org/10.1109/ISCA.2012.6237001

Impulse: building a smarter memory controller
conference, August 2002


Processing in memory: the Terasys massively parallel PIM array
journal, April 1995


Computational RAM: implementing processors in memory
journal, January 1999


Near memory data structure rearrangement
conference, October 2015

  • Gokhale, Maya; Lloyd, Scott; Hajas, Chris
  • MEMSYS '15: International Symposium on Memory Systems, Proceedings of the 2015 International Symposium on Memory Systems
  • https://doi.org/10.1145/2818950.2818986

HARD: Hardware-Assisted Lockset-based Race Detection
conference, February 2007


Deep packet inspection using parallel Bloom filters
conference, January 2003


Hardware transactional memory for GPU architectures
conference, January 2011

  • Fung, Wilson W. L.; Singh, Inderpreet; Brownsword, Andrew
  • Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-44 '11
  • https://doi.org/10.1145/2155620.2155655

Biosequence Similarity Search on the Mercury System
journal, July 2007

  • Krishnamurthy, Praveen; Buhler, Jeremy; Chamberlain, Roger
  • The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Vol. 49, Issue 1
  • https://doi.org/10.1007/s11265-007-0087-0

Space/time trade-offs in hash coding with allowable errors
journal, July 1970