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Title: Asynchronous cache flushing

Abstract

Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to, in response to a memory request issued prior to completion of the proactive flush operation, interrupt the proactive flush operation and perform a reactive flush operation to flush requested data from the first memory to the second memory.

Inventors:
; ;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1531357
Patent Number(s):
10,049,044
Application Number:
15/181,415
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
DOE Contract Number:  
AC52-07NA27344; B600716
Resource Type:
Patent
Resource Relation:
Patent File Date: 2016-06-14
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Boyer, Michael, Loh, Gabriel H., and Jayasena, Nuwan S. Asynchronous cache flushing. United States: N. p., 2018. Web.
Boyer, Michael, Loh, Gabriel H., & Jayasena, Nuwan S. Asynchronous cache flushing. United States.
Boyer, Michael, Loh, Gabriel H., and Jayasena, Nuwan S. Tue . "Asynchronous cache flushing". United States. https://www.osti.gov/servlets/purl/1531357.
@article{osti_1531357,
title = {Asynchronous cache flushing},
author = {Boyer, Michael and Loh, Gabriel H. and Jayasena, Nuwan S.},
abstractNote = {Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to, in response to a memory request issued prior to completion of the proactive flush operation, interrupt the proactive flush operation and perform a reactive flush operation to flush requested data from the first memory to the second memory.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {8}
}

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Works referenced in this record:

Resizable and relocatable memory scratch pad as a cache slice
patent, October 1999


Detection and mitigation of timing side-channel attacks
patent, September 2016