Asynchronous cache flushing
Abstract
Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to, in response to a memory request issued prior to completion of the proactive flush operation, interrupt the proactive flush operation and perform a reactive flush operation to flush requested data from the first memory to the second memory.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1531357
- Patent Number(s):
- 10049044
- Application Number:
- 15/181,415
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC52-07NA27344; B600716
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2016-06-14
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Boyer, Michael, Loh, Gabriel H., and Jayasena, Nuwan S. Asynchronous cache flushing. United States: N. p., 2018.
Web.
Boyer, Michael, Loh, Gabriel H., & Jayasena, Nuwan S. Asynchronous cache flushing. United States.
Boyer, Michael, Loh, Gabriel H., and Jayasena, Nuwan S. Tue .
"Asynchronous cache flushing". United States. https://www.osti.gov/servlets/purl/1531357.
@article{osti_1531357,
title = {Asynchronous cache flushing},
author = {Boyer, Michael and Loh, Gabriel H. and Jayasena, Nuwan S.},
abstractNote = {Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to, in response to a memory request issued prior to completion of the proactive flush operation, interrupt the proactive flush operation and perform a reactive flush operation to flush requested data from the first memory to the second memory.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {8}
}
Works referenced in this record:
Causal ladder mechanism for proactive problem determination, avoidance and recovery
patent-application, November 2007
- Subramanian, Balan; Chalasani, Nanchariah Raghuveera; Rahman, Javed
- US Patent Application 11/438875; 20070276631
Flushing Entries in a Non-Coherent Cache
patent-application, September 2014
- Hong, Sungpack; Chafi, Hassan; Sedlar, Eric
- US Patent Application 13/791863; 20140258637
Cache Memory and Cache Memory Control Unit
patent-application, December 2012
- Hirao, Taichi; Sakaguchi, Hiroaki; Yoshikawa, Hiroshi
- US Patent Application 13/515315; 20120331234
Resizable and relocatable memory scratch pad as a cache slice
patent, October 1999
- Mohamed, Moataz A.; Park, Heonchul
- US Patent Document 5,966,734
Detection and mitigation of timing side-channel attacks
patent, September 2016
- Pohlack, Martin T.
- US Patent Document 9,436,603
Fast L1 Flush Mechanism
patent-application, September 2010
- Keller, James B.; Yeh, Tse-Yu; Gunna, Ramesh
- US Patent Application 12/785842; 20100235670