Compiler-generated memory mapping hints

Title: Compiler-generated memory mapping hints

Abstract

According to one embodiment, a method of creating compiler-generated memory mapping hints in a computer system includes analyzing code, by a compiler of the computer system, to identify data access patterns in the code. System configuration information defining data processing system characteristics of a target system for the code is accessed. The data processing system characteristics include a plurality of processing resources and memory domain characteristics relative to the processing resources. A preferred allocation of data in memory domains of the target system is determined based on mapping the code to one or more selected processing resources and mapping the data to one or more of the memory domains based on the memory domain characteristics relative to the one or more selected processing resources. The preferred allocation is stored as compiler-generated memory mapping hints in a format accessible by a physical memory mapping resource of the target system.

Inventors:: O'Brien, Kathryn M.; O'Brien, John K.; Sura, Zehra N.

Issue Date:: 2019-03-05

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1525021

Patent Number(s):: 10223260

Application Number:: 14/219,136

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/10 - Address translation
G06F2212/657 - Virtual address space management
G06F12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
Y02D10/00 - Energy efficient computing

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F2212/251 - Local memory within processor subsystem

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DOE Contract Number:: B599858

Resource Type:: Patent

Resource Relation:: Patent File Date: 2014-03-19

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    O'Brien, Kathryn M., O'Brien, John K., and Sura, Zehra N. Compiler-generated memory mapping hints.  United States: N. p., 2019. 
        Web.

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                    O'Brien, Kathryn M., O'Brien, John K., & Sura, Zehra N. Compiler-generated memory mapping hints.  United States.

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                    O'Brien, Kathryn M., O'Brien, John K., and Sura, Zehra N. Tue .  
        "Compiler-generated memory mapping hints".  United States.  https://www.osti.gov/servlets/purl/1525021.

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@article{osti_1525021,

  title        = {Compiler-generated memory mapping hints},

  author       = {O'Brien, Kathryn M. and O'Brien, John K. and Sura, Zehra N.},

  abstractNote = {According to one embodiment, a method of creating compiler-generated memory mapping hints in a computer system includes analyzing code, by a compiler of the computer system, to identify data access patterns in the code. System configuration information defining data processing system characteristics of a target system for the code is accessed. The data processing system characteristics include a plurality of processing resources and memory domain characteristics relative to the processing resources. A preferred allocation of data in memory domains of the target system is determined based on mapping the code to one or more selected processing resources and mapping the data to one or more of the memory domains based on the memory domain characteristics relative to the one or more selected processing resources. The preferred allocation is stored as compiler-generated memory mapping hints in a format accessible by a physical memory mapping resource of the target system.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {3}

}

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Works referenced in this record:

Locality manager having memory and independent code, bus interface logic, and synchronization components for a processing element for intercommunication in a latency tolerant multiple processor
patent, March 1997

Casavant, Thomas L.; Fineberg, Samuel A.; Bright, Devin L.
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patent, September 2001

Stevens, Luis F.
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Methods and arrangements to manage on-chip memory to reduce memory latency
patent, April 2011

Da Silva, Dilma Menezes; Elnozahy, Elmootazbellah; Krieger, Orran
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System and method for recompiling code based on locality domain and thread affinity in NUMA computer systems
patent, May 2013

Mannarswamy, Sandya Srivilliputtur; Mehta, Virendra Kumar; Raghavendra, Prakash Sathyanath
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URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8453132

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Similar Records

Title: Compiler-generated memory mapping hints

Abstract

Citation Formats

Locality manager having memory and independent code, bus interface logic, and synchronization components for a processing element for intercommunication in a latency tolerant multiple processor patent, March 1997

Method, system and computer program product for managing memory in a non-uniform memory access system patent, September 2001

Methods and arrangements to manage on-chip memory to reduce memory latency patent, April 2011

System and method for recompiling code based on locality domain and thread affinity in NUMA computer systems patent, May 2013

Locality manager having memory and independent code, bus interface logic, and synchronization components for a processing element for intercommunication in a latency tolerant multiple processor
patent, March 1997

Method, system and computer program product for managing memory in a non-uniform memory access system
patent, September 2001

Methods and arrangements to manage on-chip memory to reduce memory latency
patent, April 2011

System and method for recompiling code based on locality domain and thread affinity in NUMA computer systems
patent, May 2013