Compiler-generated memory mapping hints

O'Brien, Kathryn M.; O'Brien, John K.; Sura, Zehra N.

Title: Compiler-generated memory mapping hints

Abstract

According to one embodiment, a method of creating compiler-generated memory mapping hints in a computer system includes analyzing code, by a compiler of the computer system, to identify data access patterns in the code. System configuration information defining data processing system characteristics of a target system for the code is accessed. The data processing system characteristics include a plurality of processing resources and memory domain characteristics relative to the processing resources. A preferred allocation of data in memory domains of the target system is determined based on mapping the code to one or more selected processing resources and mapping the data to one or more of the memory domains based on the memory domain characteristics relative to the one or more selected processing resources. The preferred allocation is stored as compiler-generated memory mapping hints in a format accessible by a physical memory mapping resource of the target system.

Inventors:: O'Brien, Kathryn M.; O'Brien, John K.; Sura, Zehra N.

Issue Date:: 2019-03-05

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1525021

Patent Number(s):: 10223260

Application Number:: 14/219,136

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/10 - Address translation
G06F2212/657 - Virtual address space management
G06F12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
Y02D10/00 - Energy efficient computing

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F2212/251 - Local memory within processor subsystem

Show less

DOE Contract Number:: B599858

Resource Type:: Patent

Resource Relation:: Patent File Date: 2014-03-19

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    O'Brien, Kathryn M., O'Brien, John K., and Sura, Zehra N. Compiler-generated memory mapping hints.  United States: N. p., 2019. 
        Web.

Copy to clipboard


                    O'Brien, Kathryn M., O'Brien, John K., & Sura, Zehra N. Compiler-generated memory mapping hints.  United States.

Copy to clipboard


                    O'Brien, Kathryn M., O'Brien, John K., and Sura, Zehra N. Tue .  
        "Compiler-generated memory mapping hints".  United States.  https://www.osti.gov/servlets/purl/1525021.

Copy to clipboard


                    
@article{osti_1525021,

  title        = {Compiler-generated memory mapping hints},

  author       = {O'Brien, Kathryn M. and O'Brien, John K. and Sura, Zehra N.},

  abstractNote = {According to one embodiment, a method of creating compiler-generated memory mapping hints in a computer system includes analyzing code, by a compiler of the computer system, to identify data access patterns in the code. System configuration information defining data processing system characteristics of a target system for the code is accessed. The data processing system characteristics include a plurality of processing resources and memory domain characteristics relative to the processing resources. A preferred allocation of data in memory domains of the target system is determined based on mapping the code to one or more selected processing resources and mapping the data to one or more of the memory domains based on the memory domain characteristics relative to the one or more selected processing resources. The preferred allocation is stored as compiler-generated memory mapping hints in a format accessible by a physical memory mapping resource of the target system.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {3}

}

Copy to clipboard

Patent:

View Patent

Save / Share:

Export Metadata

Save to My Library

Works referenced in this record:

Locality manager having memory and independent code, bus interface logic, and synchronization components for a processing element for intercommunication in a latency tolerant multiple processor
patent, March 1997

Casavant, Thomas L.; Fineberg, Samuel A.; Bright, Devin L.
US Patent Document 5,613,136
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5613136

Method, system and computer program product for managing memory in a non-uniform memory access system
patent, September 2001

Stevens, Luis F.
US Patent Document 6,289,424
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6289424

Methods and arrangements to manage on-chip memory to reduce memory latency
patent, April 2011

Da Silva, Dilma Menezes; Elnozahy, Elmootazbellah; Krieger, Orran
US Patent Document 7,934,061
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7934061

System and method for recompiling code based on locality domain and thread affinity in NUMA computer systems
patent, May 2013

Mannarswamy, Sandya Srivilliputtur; Mehta, Virendra Kumar; Raghavendra, Prakash Sathyanath
US Patent Document 8,453,132
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8453132

Similar Records in DOE Patents and OSTI.GOV collections:

Using predictions of outcomes of cache memory access requests for controlling whether a request generator sends memory access requests to a memory in parallel with cache memory access requests

Patent Yin, Jieming; Eckert, Yasuko; Poremba, Matthew R.; ...

An electronic device handles memory access requests for data in a memory. The electronic device includes a memory controller for the memory, a last-level cache memory, a request generator, and a predictor. The predictor determines a likelihood that a cache memory access request for data at a given address will hit in the last-level cache memory. Based on the likelihood, the predictor determines: whether a memory access request is to be sent by the request generator to the memory controller for the data in parallel with the cache memory access request being resolved in the last-level cache memory, and, whenmore » « less
Full Text Available
Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests

Patent Gala, Alan; Ohmacht, Martin

A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memorymore » « less
Full Text Available
Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

Patent Ohmacht, Martin

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.
Full Text Available
Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

Patent Ohmacht, Martin

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.
Full Text Available
Secure true random number generation using 1.5-T transistor flash memory

Patent Clark, Lawrence T.; Adams, James; Holbert, Keith E.

This disclosure relates generally to physically unclonable function (PUF) circuitry along with methods of generating numbers. In one embodiment, the PUF circuitry includes a memory, a memory control circuitry, and whitening circuitry. To reduce or eliminate the systematic bias from the array, whitening circuitry is configured to generate a random number comprising random number bits in response to the memory control circuit implementing at least one sequence of memory cycles on the array of the memory cells in the memory. The whitening circuitry is configured to provide the random number bits of the random number based on the variable bitmore » « less
Full Text Available

Similar Records

Title: Compiler-generated memory mapping hints

Abstract

Citation Formats

Locality manager having memory and independent code, bus interface logic, and synchronization components for a processing element for intercommunication in a latency tolerant multiple processor patent, March 1997

Method, system and computer program product for managing memory in a non-uniform memory access system patent, September 2001

Methods and arrangements to manage on-chip memory to reduce memory latency patent, April 2011

System and method for recompiling code based on locality domain and thread affinity in NUMA computer systems patent, May 2013

Locality manager having memory and independent code, bus interface logic, and synchronization components for a processing element for intercommunication in a latency tolerant multiple processor
patent, March 1997

Method, system and computer program product for managing memory in a non-uniform memory access system
patent, September 2001

Methods and arrangements to manage on-chip memory to reduce memory latency
patent, April 2011

System and method for recompiling code based on locality domain and thread affinity in NUMA computer systems
patent, May 2013