Title: Method for simultaneous modification of multiple semiconductor device features

Abstract

Various technologies for simultaneously making a plurality of modifications to a previously manufactured semiconductor are described herein. A mask layer is applied to a surface of the previously manufactured semiconductor device. A pattern is formed in the mask layer, where the pattern is aligned with a plurality of features of the semiconductor device that are desirably modified. Layers of the semiconductor device are etched based on the pattern to create a plurality of vias that each extend through one or more layers of the semiconductor device to a respective feature of the device. A conducting material is deposited into the vias to form a plurality of conducting plugs. Conducting material may be further deposited on the surface of the semiconductor device to connect plugs to one another and/or connect plugs to surface features of the device, thereby forming a plurality of new connections between features of the semiconductor device.

Inventors:

Shul, Randy J.; Sniegowski, Jeffry J.; Larson, Kurt W.; Zortman, William A.

Issue Date:

2019-02-26

Research Org.:

Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1524991

Patent Number(s):

10217704

Application Number:

15/794,403

Assignee:

National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)

Patent Classifications (CPCs):

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

H01L21/475 - using masks
H01L21/76898 - {formed through a semiconductor substrate}
H01L21/486 - {Via connections through the substrate with or without pins}
H01L21/76892 - {modifying the pattern}
H01L23/49827 - {Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
H01L21/76805 - {the opening being a via or contact hole penetrating the underlying conductor}
H01L21/31144 - {using masks}
H01L21/308 - using masks

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F30/00 - Computer-aided design [CAD]

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

H01L23/5226 - {Via connections in a multilevel interconnection structure}

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DOE Contract Number:  

NA0003525

Resource Type:

Patent

Resource Relation:

Patent File Date: 2017-10-26

Country of Publication:

United States

Language:

English

Subject:

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SUPERFLUIDITY