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Title: Method for simultaneous modification of multiple semiconductor device features

Abstract

Various technologies for simultaneously making a plurality of modifications to a previously manufactured semiconductor are described herein. A mask layer is applied to a surface of the previously manufactured semiconductor device. A pattern is formed in the mask layer, where the pattern is aligned with a plurality of features of the semiconductor device that are desirably modified. Layers of the semiconductor device are etched based on the pattern to create a plurality of vias that each extend through one or more layers of the semiconductor device to a respective feature of the device. A conducting material is deposited into the vias to form a plurality of conducting plugs. Conducting material may be further deposited on the surface of the semiconductor device to connect plugs to one another and/or connect plugs to surface features of the device, thereby forming a plurality of new connections between features of the semiconductor device.

Inventors:
; ; ;
Issue Date:
Research Org.:
National Technology & Engineering Solutions of Sandia, LLC, Albuquerque, NM (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1524991
Patent Number(s):
10,217,704
Application Number:
15/794,403
Assignee:
National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
DOE Contract Number:  
NA0003525
Resource Type:
Patent
Resource Relation:
Patent File Date: 2017-10-26
Country of Publication:
United States
Language:
English
Subject:
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SUPERFLUIDITY

Citation Formats

Shul, Randy J., Sniegowski, Jeffry J., Larson, Kurt W., and Zortman, William A. Method for simultaneous modification of multiple semiconductor device features. United States: N. p., 2019. Web.
Shul, Randy J., Sniegowski, Jeffry J., Larson, Kurt W., & Zortman, William A. Method for simultaneous modification of multiple semiconductor device features. United States.
Shul, Randy J., Sniegowski, Jeffry J., Larson, Kurt W., and Zortman, William A. Tue . "Method for simultaneous modification of multiple semiconductor device features". United States. https://www.osti.gov/servlets/purl/1524991.
@article{osti_1524991,
title = {Method for simultaneous modification of multiple semiconductor device features},
author = {Shul, Randy J. and Sniegowski, Jeffry J. and Larson, Kurt W. and Zortman, William A.},
abstractNote = {Various technologies for simultaneously making a plurality of modifications to a previously manufactured semiconductor are described herein. A mask layer is applied to a surface of the previously manufactured semiconductor device. A pattern is formed in the mask layer, where the pattern is aligned with a plurality of features of the semiconductor device that are desirably modified. Layers of the semiconductor device are etched based on the pattern to create a plurality of vias that each extend through one or more layers of the semiconductor device to a respective feature of the device. A conducting material is deposited into the vias to form a plurality of conducting plugs. Conducting material may be further deposited on the surface of the semiconductor device to connect plugs to one another and/or connect plugs to surface features of the device, thereby forming a plurality of new connections between features of the semiconductor device.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {2}
}

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Works referenced in this record:

Electron beam modification of CVD deposited low dielectric constant materials
patent, June 2003


IC modification with focused ion beam system
patent, August 1992


Semiconductor memory device and method of manufacturing the same
patent, December 2005


Reactive ion etching for semiconductor device feature topography modification
patent, December 2009