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Title: Encoding data within a crossbar memory array

Abstract

In an example, in a method for encoding data within a crossbar memory array containing cells, bits of input data may be received. The received bits of data may be mapped to the cells in a row of the memory array, in which the cells are to be assigned to one of a low resistance state and a high resistance state. A subset of the mapped bits in the row may be grouped into a word pattern. The word pattern may be arranged such that more low resistance states are mapped to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.

Inventors:
; ;
Issue Date:
Research Org.:
Hewlett Packard Enterprise Development LP, Houston, TX (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1495674
Patent Number(s):
10175906
Application Number:
15/325,118
Assignee:
Hewlett Packard Enterprise Development LP (Houston, TX)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
DOE Contract Number:  
SC0005026
Resource Type:
Patent
Resource Relation:
Patent File Date: 2014 Jul 31
Country of Publication:
United States
Language:
English

Citation Formats

Muralimanohar, Naveen, Ordentlich, Erik, and Xu, Cong. Encoding data within a crossbar memory array. United States: N. p., 2019. Web.
Muralimanohar, Naveen, Ordentlich, Erik, & Xu, Cong. Encoding data within a crossbar memory array. United States.
Muralimanohar, Naveen, Ordentlich, Erik, and Xu, Cong. Tue . "Encoding data within a crossbar memory array". United States. https://www.osti.gov/servlets/purl/1495674.
@article{osti_1495674,
title = {Encoding data within a crossbar memory array},
author = {Muralimanohar, Naveen and Ordentlich, Erik and Xu, Cong},
abstractNote = {In an example, in a method for encoding data within a crossbar memory array containing cells, bits of input data may be received. The received bits of data may be mapped to the cells in a row of the memory array, in which the cells are to be assigned to one of a low resistance state and a high resistance state. A subset of the mapped bits in the row may be grouped into a word pattern. The word pattern may be arranged such that more low resistance states are mapped to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {1}
}

Works referenced in this record:

Sneak-path constraints in memristor crossbar arrays
conference, July 2013


Processor-Based Apparatus and Method for Processing Bit Streams
patent-application, December 2013


Apparatus and method for memory operations using address-dependent conditions
patent, May 2007


Setting threshold voltages of cells in a memory block to reduce leakage in the memory block
patent, August 2009


Three-device non-volatile memory cell
patent, December 2013