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Title: Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

Abstract

A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

Inventors:
;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1495669
Patent Number(s):
10176281
Application Number:
14/939,411
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
B554331
Resource Type:
Patent
Resource Relation:
Patent File Date: 2015 Nov 12
Country of Publication:
United States
Language:
English

Citation Formats

Asaad, Sameh W., and Kapur, Mohit. Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator. United States: N. p., 2019. Web.
Asaad, Sameh W., & Kapur, Mohit. Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator. United States.
Asaad, Sameh W., and Kapur, Mohit. Tue . "Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator". United States. https://www.osti.gov/servlets/purl/1495669.
@article{osti_1495669,
title = {Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator},
author = {Asaad, Sameh W. and Kapur, Mohit},
abstractNote = {A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {1}
}

Works referenced in this record:

Hierarchical, network-based emulation system
patent-application, December 2004


A Reprogrammable EDGE Baseband and Multimedia Handset SoC With 6-Mbit Embedded DRAM
journal, January 2006


Method and Apparatus to Debug an Integrated Circuit Chip Via Synchronous Clock Stop and Scan
patent-application, January 2009


Simulation Apparatus and Control Method of Simulation
patent-application, March 2009


Processor/memory co-exploration at multiple abstraction levels
patent, August 2010


Processing system with interspersed stall propagating processors and communication elements
patent, August 2008


Clock Encoded Pre-Fetch to Access Memory Data in Clustering Network Environment
patent-application, June 2009


Peak Power Detection in Digital Design Using Emulation Systems
patent-application, October 2009


Testing of an integrated circuit having an embedded processor
patent, September 2007


System and method of mapping memory blocks in a configurable integrated circuit
patent, September 2009


Clock generation system for a prototyping apparatus
patent-application, April 2003


Method of programming a co-verification system
patent-application, January 2006


Method and apparatus for test generation during circuit design
patent-application, June 2002


Time multiplexed programmable logic device
patent, July 1997


Circuit testing with ring-connected test instrument modules
patent-application, June 2003


Resource board for emulation system
patent-application, December 2004


Input/output multiplexer bus
patent, November 2011


Method and apparatus for emulation of logic circuits
patent-application, July 2005


Logic verification system
patent-application, April 2004


Method and System for Design Verification of Electronic Circuits
patent-application, August 2002


Intel® atom™ processor core made FPGA-synthesizable
conference, January 2009


Automatic hidden refresh in a dram and method therefor
patent-application, December 2005


Memory-Based Trigger Generation Scheme in an Emulation Environment
patent-application, September 2010


Memory controller architecture
patent, September 2000


Memory Controller Interface
patent-application, January 2010


Wire Like Link for Cycle Reproducible and Cycle Accurate Hardware Accelerator
patent-application, July 2013


Behavior processor system and method
patent-application, June 2006


FPGA Simulated Annealing Accelerator
patent-application, December 2009


Cycle Accurate and Cycle Reproducible Memory for an FPGA Based Hardware Accelerator
patent-application, December 2013


A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation
conference, January 2012


Techniques For Use With Automated Circuit Design and Simulations
patent-application, December 2008


Clock distribution in a circuit emulator
patent-application, June 2005


Media cross conversion interface
patent-application, March 2003


Efficient Testbench Code Synthesis for a Hardware Emulator System
conference, April 2007


Clock distribution to facilitate gated clocks
patent, November 2011


Memory Randomization for Protection Against Side Channel Attacks
patent-application, April 2009


Method and circuit for rapid alignment of signals
patent-application, June 2008


Apparatus and system for implementing variable speed scan testing
patent-application, February 2012


Generating user clocks for a prototyping environment
patent, November 2013