Title: Combined group ECC protection and subgroup parity protection

Abstract

A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.

Inventors:

Gara, Alan; Chen, Dong; Heidelberger, Philip; Ohmacht, Martin

Issue Date:

2018-11-27

Research Org.:

International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1495212

Patent Number(s):

10140179

Application Number:

14/973,021

Assignee:

International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F2212/403 - Error protection encoding, e.g. using parity or ECC codes

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING

H03M13/29 - combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H03M13/616 - {Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations}
H03M13/271 - {Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations}

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F11/1076 - {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING

H03M1/0687 - {using fault-tolerant coding, e.g. parity check, error correcting codes

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F11/1064 - {in cache or content addressable memories}

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING

H03M13/2707 - {Simple row-column interleaver, i.e. pure block interleaving}
H03M13/13 - Linear codes

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DOE Contract Number:  

B554331

Resource Type:

Patent

Resource Relation:

Patent File Date: 2015 Dec 17

Country of Publication:

United States

Language:

English

Subject:

97 MATHEMATICS AND COMPUTING