Combined group ECC protection and subgroup parity protection

Gara, Alan; Chen, Dong; Heidelberger, Philip; Ohmacht, Martin

Title: Combined group ECC protection and subgroup parity protection

Abstract

A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.

Inventors:: Gara, Alan; Chen, Dong; Heidelberger, Philip; Ohmacht, Martin

Issue Date:: 2018-11-27

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1495212

Patent Number(s):: 10140179

Application Number:: 14/973,021

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/1064 - {in cache or content addressable memories}
G06F11/1076 - {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}
G06F2212/403 - Error protection encoding, e.g. using parity or ECC codes

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING
H03M1/0687 - {using fault-tolerant coding, e.g. parity check, error correcting codes
H03M13/13 - Linear codes
H03M13/2707 - {Simple row-column interleaver, i.e. pure block interleaving}
H03M13/271 - {Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations}
H03M13/29 - combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H03M13/616 - {Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations}

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DOE Contract Number:: B554331

Resource Type:: Patent

Resource Relation:: Patent File Date: 2015 Dec 17

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Gara, Alan, Chen, Dong, Heidelberger, Philip, and Ohmacht, Martin. Combined group ECC protection and subgroup parity protection.  United States: N. p., 2018. 
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                    Gara, Alan, Chen, Dong, Heidelberger, Philip, & Ohmacht, Martin. Combined group ECC protection and subgroup parity protection.  United States.

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                    Gara, Alan, Chen, Dong, Heidelberger, Philip, and Ohmacht, Martin. Tue .  
        "Combined group ECC protection and subgroup parity protection".  United States.  https://www.osti.gov/servlets/purl/1495212.

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@article{osti_1495212,

  title        = {Combined group ECC protection and subgroup parity protection},

  author       = {Gara, Alan and Chen, Dong and Heidelberger, Philip and Ohmacht, Martin},

  abstractNote = {A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2018},

  month        = {11}

}

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Title: Combined group ECC protection and subgroup parity protection

Abstract

Citation Formats

Disk drive with cache controlled adaptively for amount of prefetch patent, March 1999

Method and apparatus for weighted fair queuing patent, May 2008

Automatic byte swap and alignment for descriptor-based direct memory access data transfers patent, September 2004

Synchronization, coherence, and event ordering in multiprocessors journal, February 1988

High speed DVD error correction engine patent, April 2004

Token-based active queue management patent, October 2007

Message transfer apparatus for controlling a message send in a packet switched interconnection network patent, February 2000

Optimization of MPI collective communication on BlueGene/L systems conference, January 2005

Distributed processing architecture with scalable processing layers patent-application, June 2003

Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques patent-application, September 2002

Snoop filter line replacement for reduction of back invalidates in multi-node architectures patent, July 2003

Credit-based scheme for high performance communication between devices in a packet-based communication system patent, August 2002

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Partitioned cache of multiple logical levels with adaptive reconfiguration based on multiple criteria patent-application, October 2002

Method, Apparatus, and Computer Program Product for a Cache Coherency Protocol State That Predicts Locations of Modified Memory Blocks patent-application, June 2008

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Intel 870: a building block for cost-effective, scalable servers journal, March 2002

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Tables with direct memory access descriptor lists for distributed direct memory access patent-application, September 2005

Multiprocessor system having controller for controlling the number of processors for which cache coherency must be guaranteed patent, October 2003

Queue manager having a multi-level arbitrator patent-application, July 2007

Partially resettable, segmented DMA counter patent, September 1995

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Memory array with precharge control circuit patent, July 2007

Dual channel helical recorder patent, August 1992

Synchronized storage providing multiple synchronization semantics patent-application, November 2005

System and method for conflict responses in a cache coherency protocol with ordering point migration patent-application, July 2005

Method and apparatus for enhancing data rate in processing ECC product-coded data arrays in DVD storage subsystems and the like patent, April 2001

Shared memory apparatus and method for multiprocessor systems patent, September 2001

Count calibration for synchronous data transfer between clock domains patent-application, November 2006

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Multilevel fair priority round robin arbiter patent, November 2006

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Credit-based flow control checking and correction system patent, October 1998

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Systems and methods for access port ICMP analysis patent-application, August 2007

Method and apparatus for striping message payload data over a network patent-application, June 2007

Dynamic request priority arbitration patent, April 2005

Cache coherency method and system employing serially encoded snoop responses patent, August 1997

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Blue Gene/L advanced diagnostics environment journal, March 2005

Fast re-synchronization of independent domain clocks after powerdown to enable fast system start-up patent, December 2003

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Computer system implementing synchronized broadcast using timestamps patent-application, February 2004

Partially inclusive snoop filter patent-application, January 2004

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Method for maintaining cache coherency in software in a shared memory system patent-application, July 2002

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Disk drive with cache controlled adaptively for amount of prefetch
patent, March 1999

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patent, May 2008

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patent, September 2004

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journal, February 1988

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patent, April 2004

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patent, October 2007

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patent, February 2000

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conference, January 2005

Distributed processing architecture with scalable processing layers
patent-application, June 2003

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patent-application, September 2002

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patent, July 2003

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patent, August 2002

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patent-application, March 2003

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patent-application, October 2002

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patent-application, June 2008

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patent, April 2011

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patent, April 2010

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patent, October 2001

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patent, April 2005

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journal, March 2002

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patent, September 1998

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patent-application, April 2006

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patent-application, September 2005

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patent, October 2003

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patent-application, July 2007

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patent, September 1995

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patent, May 2003

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patent, July 2007

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patent, August 1992

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patent-application, November 2005

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patent-application, July 2005

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patent, April 2001

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patent, September 2001

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patent-application, November 2006

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patent, April 2004

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patent, November 2006

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patent-application, July 2007

System, architecture, and method for logical server and other network devices in a dynamically configurable multi-server network environment
patent, June 2006

Credit-based flow control checking and correction system
patent, October 1998

Method for verifying clock signal frequency of computer sound interface
patent-application, October 2003

Use of code vectors for frame forwarding in a bridge/router
patent, February 2001

Method and apparatus of allocating minimum and maximum bandwidths on a bus-based communication system
patent, June 2006

ATM reassembly controller and method
patent, June 1999

Method and system for servicing cache line in response to partial cache line request
patent-application, July 2002

Multiple-capture DFT system for scan-based integrated circuits
patent, October 2005

Method and apparatus for detecting pipeline address conflict using parallel compares of multiple real addresses
patent-application, September 2003

Apparatus for transferring blocks of information from one node to a second node in a computer network
patent, October 1988

Method, system, and program for remote resource management
patent, April 2008

Systems and methods for access port ICMP analysis
patent-application, August 2007

Method and apparatus for striping message payload data over a network
patent-application, June 2007

Dynamic request priority arbitration
patent, April 2005

Cache coherency method and system employing serially encoded snoop responses
patent, August 1997

Novel massively parallel supercomputer
patent-application, May 2004

Method and system for fast data access using a memory array
patent-application, March 2007

Write combining buffer that supports snoop request
patent, April 2002

Blue Gene/L advanced diagnostics environment
journal, March 2005

Fast re-synchronization of independent domain clocks after powerdown to enable fast system start-up
patent, December 2003

Data processor
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patent, June 2000

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patent-application, March 2003

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patent-application, March 2005

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patent-application, January 2005

Mapping memory in a parallel processing environment
patent, November 2009

Computer system implementing synchronized broadcast using timestamps
patent-application, February 2004

Partially inclusive snoop filter
patent-application, January 2004

Multimedia system and method of controlling data transfer between a host system and a network adapter using a DMA engine
patent, January 1998

DMA engine for protocol processing
patent-application, September 2006

System and method for checking validity of data transmission
patent-application, March 2006

Semiconductor integrated circuit with delay test circuit, and method for testing semiconductor integrated circuit
patent, November 2009

Methods of transmitting data packets without exceeding a maximum queue time period and related devices
patent-application, December 2003

Method and systems for flow control of transmissions over channel-based switched fabric connections
patent, May 2004

Synchronous parallel system for emulation and discrete event simulation
patent, November 2001

On chip network with independent logical and physical layers
patent-application, January 2004

Mechanism for delivering interrupt messages
patent, July 2001

Method for maintaining cache coherency in software in a shared memory system
patent-application, July 2002

Independent computer storage addressing in input/output transfers
patent, May 1997

Network DMA method
patent, August 2004

Directory-based cache coherence in large-scale multiprocessors
journal, June 1990

Multiple clock rate test apparatus for testing digital systems
patent, September 1994