Combined group ECC protection and subgroup parity protection
Abstract
A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corporation, Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1495212
- Patent Number(s):
- 10,140,179
- Application Number:
- 14/973,021
- Assignee:
- International Business Machines Corporation (Armonk, NY) OSTI
- DOE Contract Number:
- B554331
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2015 Dec 17
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Gara, Alan, Chen, Dong, Heidelberger, Philip, and Ohmacht, Martin. Combined group ECC protection and subgroup parity protection. United States: N. p., 2018.
Web.
Gara, Alan, Chen, Dong, Heidelberger, Philip, & Ohmacht, Martin. Combined group ECC protection and subgroup parity protection. United States.
Gara, Alan, Chen, Dong, Heidelberger, Philip, and Ohmacht, Martin. Tue .
"Combined group ECC protection and subgroup parity protection". United States. https://www.osti.gov/servlets/purl/1495212.
@article{osti_1495212,
title = {Combined group ECC protection and subgroup parity protection},
author = {Gara, Alan and Chen, Dong and Heidelberger, Philip and Ohmacht, Martin},
abstractNote = {A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {11}
}
Works referenced in this record:
Multiprocessor system having controller for controlling the number of processors for which cache coherency must be guaranteed
patent, October 2003
- Morioka, Michio; Kurosawa, Kenichi; Nakamikawa, Tetsuaki
- US Patent Document 6,631,447