Combined group ECC protection and subgroup parity protection

Gara, Alan; Chen, Dong; Heidelberger, Philip; Ohmacht, Martin

Title: Combined group ECC protection and subgroup parity protection

Abstract

A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.

Inventors:: Gara, Alan; Chen, Dong; Heidelberger, Philip; Ohmacht, Martin

Issue Date:: 2018-11-27

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1495212

Patent Number(s):: 10140179

Application Number:: 14/973,021

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F2212/403 - Error protection encoding, e.g. using parity or ECC codes

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING
H03M13/29 - combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H03M13/616 - {Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations}
H03M13/271 - {Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations}

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/1076 - {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING
H03M1/0687 - {using fault-tolerant coding, e.g. parity check, error correcting codes

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/1064 - {in cache or content addressable memories}

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING
H03M13/2707 - {Simple row-column interleaver, i.e. pure block interleaving}
H03M13/13 - Linear codes

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DOE Contract Number:: B554331

Resource Type:: Patent

Resource Relation:: Patent File Date: 2015 Dec 17

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Gara, Alan, Chen, Dong, Heidelberger, Philip, and Ohmacht, Martin. Combined group ECC protection and subgroup parity protection.  United States: N. p., 2018. 
        Web.

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                    Gara, Alan, Chen, Dong, Heidelberger, Philip, & Ohmacht, Martin. Combined group ECC protection and subgroup parity protection.  United States.

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                    Gara, Alan, Chen, Dong, Heidelberger, Philip, and Ohmacht, Martin. Tue .  
        "Combined group ECC protection and subgroup parity protection".  United States.  https://www.osti.gov/servlets/purl/1495212.

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@article{osti_1495212,

  title        = {Combined group ECC protection and subgroup parity protection},

  author       = {Gara, Alan and Chen, Dong and Heidelberger, Philip and Ohmacht, Martin},

  abstractNote = {A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2018},

  month        = {11}

}

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Works referenced in this record:

Synchronization, coherence, and event ordering in multiprocessors
journal, February 1988

Dubois, M.; Scheurich, C.; Briggs, F. A.
Computer, Vol. 21, Issue 2
https://doi.org/10.1109/2.15

Optimization of MPI collective communication on BlueGene/L systems
conference, January 2005

Almási, George; Heidelberger, Philip; Archer, Charles J.
Proceedings of the 19th annual international conference on Supercomputing - ICS '05
https://doi.org/10.1145/1088149.1088183

Intel 870: a building block for cost-effective, scalable servers
journal, March 2002

Briggs, F.; Cekleov, M.; Creta, K.
IEEE Micro, Vol. 22, Issue 2
https://doi.org/10.1109/MM.2002.997878

Blue Gene/L advanced diagnostics environment
journal, March 2005

Giampapa, M. E.; Bellofatto, R.; Blumrich, M. A.
IBM Journal of Research and Development, Vol. 49, Issue 2.3
https://doi.org/10.1147/rd.492.0319

Directory-based cache coherence in large-scale multiprocessors
journal, June 1990

Chaiken, D.; Fields, C.; Kurihara, K.
Computer, Vol. 23, Issue 6
https://doi.org/10.1109/2.55500

Performance evaluation of adaptive MPI
conference, January 2006

Huang, Chao; Zheng, Gengbin; Kalé, Laxmikant
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '06
https://doi.org/10.1145/1122971.1122976

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
journal, August 2005

Pande, P. P.; Grecu, C.; Jones, M.
IEEE Transactions on Computers, Vol. 54, Issue 8
https://doi.org/10.1109/TC.2005.134

Overview of the Blue Gene/L system architecture
journal, March 2005

Gara, A.; Blumrich, M. A.; Chen, D.
IBM Journal of Research and Development, Vol. 49, Issue 2.3
https://doi.org/10.1147/rd.492.0195

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Title: Combined group ECC protection and subgroup parity protection

Abstract

Citation Formats

Synchronization, coherence, and event ordering in multiprocessors journal, February 1988

Optimization of MPI collective communication on BlueGene/L systems conference, January 2005

Intel 870: a building block for cost-effective, scalable servers journal, March 2002

Blue Gene/L advanced diagnostics environment journal, March 2005

Directory-based cache coherence in large-scale multiprocessors journal, June 1990

Performance evaluation of adaptive MPI conference, January 2006

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures journal, August 2005

Overview of the Blue Gene/L system architecture journal, March 2005

Synchronization, coherence, and event ordering in multiprocessors
journal, February 1988

Optimization of MPI collective communication on BlueGene/L systems
conference, January 2005

Intel 870: a building block for cost-effective, scalable servers
journal, March 2002

Blue Gene/L advanced diagnostics environment
journal, March 2005

Directory-based cache coherence in large-scale multiprocessors
journal, June 1990

Performance evaluation of adaptive MPI
conference, January 2006

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
journal, August 2005

Overview of the Blue Gene/L system architecture
journal, March 2005