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Title: Multiple core computer processor with globally-accessible local memories

Abstract

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.

Inventors:
; ;
Issue Date:
Research Org.:
Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1489513
Patent Number(s):
10,102,179
Application Number:
15/243,634
Assignee:
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA (Oakland, CA)
DOE Contract Number:  
AC02-05CH11231
Resource Type:
Patent
Resource Relation:
Patent File Date: 2016 Aug 22
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Shalf, John, Donofrio, David, and Oliker, Leonid. Multiple core computer processor with globally-accessible local memories. United States: N. p., 2018. Web.
Shalf, John, Donofrio, David, & Oliker, Leonid. Multiple core computer processor with globally-accessible local memories. United States.
Shalf, John, Donofrio, David, and Oliker, Leonid. Tue . "Multiple core computer processor with globally-accessible local memories". United States. https://www.osti.gov/servlets/purl/1489513.
@article{osti_1489513,
title = {Multiple core computer processor with globally-accessible local memories},
author = {Shalf, John and Donofrio, David and Oliker, Leonid},
abstractNote = {A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {10}
}

Patent:

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Works referenced in this record:

Energy-Efficient Computing for Extreme-Scale Science
journal, November 2009

  • Donofrio, David; Oliker, Leonid; Shalf, John
  • Computer, Vol. 42, Issue 11
  • DOI: 10.1109/MC.2009.353