Multiple core computer processor with globally-accessible local memories
Abstract
A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1489513
- Patent Number(s):
- 10102179
- Application Number:
- 15/243,634
- Assignee:
- THE REGENTS OF THE UNIVERSITY OF CALIFORNIA (Oakland, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
- DOE Contract Number:
- AC02-05CH11231
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2016 Aug 22
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Shalf, John, Donofrio, David, and Oliker, Leonid. Multiple core computer processor with globally-accessible local memories. United States: N. p., 2018.
Web.
Shalf, John, Donofrio, David, & Oliker, Leonid. Multiple core computer processor with globally-accessible local memories. United States.
Shalf, John, Donofrio, David, and Oliker, Leonid. Tue .
"Multiple core computer processor with globally-accessible local memories". United States. https://www.osti.gov/servlets/purl/1489513.
@article{osti_1489513,
title = {Multiple core computer processor with globally-accessible local memories},
author = {Shalf, John and Donofrio, David and Oliker, Leonid},
abstractNote = {A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Oct 16 00:00:00 EDT 2018},
month = {Tue Oct 16 00:00:00 EDT 2018}
}
Works referenced in this record:
Managing cache memory in a parallel processing environment
patent, February 2011
- Wentzlaff, David; Mattina, Matthew; Agarwal, Anant
- US Patent Document 7,882,307
Distributed home-node hub
patent, April 2013
- Sivaramakrishnan, Ramaswamy; Phillips, Stephen E.
- US Patent Document 8,429,353
Near neighbor data cache sharing
patent, May 2014
- Comparan, Miguel; Shearer, Robert A.
- US Patent Document 8,719,508
Systems and methods for a fast interconnect table
patent, December 2014
- Lethin, Richard A.; Ros-Giralt, Jordi; Szilagyi, Peter
- US Patent Document 8,914,601
Multi-core processor system, cache coherency control method, and computer product
patent, March 2015
- Suzuki, Takahisa; Yamashita, Koichiro; Yamauchi, Hiromasa
- US Patent Document 8,996,820
Shared load-store unit to monitor network activity and external memory transaction status for thread switching
patent, May 2015
- McConnell, Ray
- US Patent Document 9,037,836
Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes
patent-application, March 2005
- Dodson, John; Fields, James; Guthrie, Guy
- US Patent Application 10/675744; 20050071573
Protocol for maintaining cache coherency in a CMP
patent-application, June 2005
- Mattina, Matthew; Chrysos, George
- US Patent Application 10/749752; 20050144390
Processor Memory System
patent-application, June 2009
- McConnell, Ray
- US Patent Application 11/573556; 20090164752
eXtreme Virtual Memory
patent-application, December 2009
- Kepner, Jeremy; Kim, Hahn; Kahn, Crystal
- US Patent Application 12/374815; 20090313449
Systems And Methods For Managing Large Cache Services In A Multi-Core System
patent-application, June 2011
- Khemani, Prakash; Kumar, Anil; Chauhan, Abhishek
- US Patent Application 12/645855; 20110153953
Advanced Processor With Mechanism For Fast Packet Queuing Operations
patent-application, October 2011
- Hass, David; Rashid, Abbas
- US Patent Application 13/084516; 20110255542
Execution Migration
patent-application, October 2011
- Devadas, Srinivas; Khan, Omer; Lis, Mieszko
- US Patent Application 13/087712; 20110258420
Microcontroller having a computing unit and a logic circuit, and method for carrying out computations by a microcontroller for a regulation or a control in a vehicle
patent-application, November 2011
- Streichert, Felix; Lang, Tobias; Markert, Heiner
- US Patent Application 13/093421; 20110282517
Control Device And Method For Calculating An Output Parameter For A Controller
patent-application, May 2013
- Streichert, Felix; Lang, Tobias; Markert, Heiner
- US Patent Application 13/643464; 20130110749
Energy-Efficient Computing for Extreme-Scale Science
journal, November 2009
- Donofrio, David; Oliker, Leonid; Shalf, John
- Computer, Vol. 42, Issue 11