Title: Hybrid memory module bridge network and buffers

Abstract

Systems, apparatuses, and methods for implementing a hybrid memory module bridge network and buffers are disclosed. A system includes one or more host processors and multiple memory modules. Each memory module includes a relatively low pin count, high-bandwidth serial link to one or more other memory modules to perform inter-memory data transfers without consuming host-memory bandwidth. In one embodiment, a first memory module acts as a cache and a second memory module acts as the main memory for the system. The traffic between the host and the first memory module utilizes a first interface, and the cache traffic between the first and second memory modules utilizes a second interface. Cache line fill and writeback transfers between the first and second memory modules occur in parallel with timing-critical cache demand accesses from the host, in a latency-tolerant and buffered manner, without interfering with the cache demand accesses.

Inventors:

Roberts, David A.

Issue Date:

2018-10-09

Research Org.:

Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1485288

Patent Number(s):

10095421

Application Number:

15/331,582

Assignee:

Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F12/0868 - Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
G06F13/14 - Handling requests for interconnection or transfer
G06F13/1684 - {using multiple buses}
G06F2212/222 - Non-volatile memory
G06F2212/311 - In host system
G06F3/0611 - {in relation to response time}
G06F3/0659 - {Command handling arrangements, e.g. command buffers, queues, command scheduling}
G06F3/0685 - {Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays}

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES

G11C7/1072 - {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}

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DOE Contract Number:  

AC52-07NA27344

Resource Type:

Patent

Resource Relation:

Patent File Date: 2016 Oct 21

Country of Publication:

United States

Language:

English

Subject:

97 MATHEMATICS AND COMPUTING