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Title: Hybrid memory module bridge network and buffers

Systems, apparatuses, and methods for implementing a hybrid memory module bridge network and buffers are disclosed. A system includes one or more host processors and multiple memory modules. Each memory module includes a relatively low pin count, high-bandwidth serial link to one or more other memory modules to perform inter-memory data transfers without consuming host-memory bandwidth. In one embodiment, a first memory module acts as a cache and a second memory module acts as the main memory for the system. The traffic between the host and the first memory module utilizes a first interface, and the cache traffic between the first and second memory modules utilizes a second interface. Cache line fill and writeback transfers between the first and second memory modules occur in parallel with timing-critical cache demand accesses from the host, in a latency-tolerant and buffered manner, without interfering with the cache demand accesses.
Inventors:
Issue Date:
OSTI Identifier:
1485288
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA) LLNL
Patent Number(s):
10,095,421
Application Number:
15/331,582
Contract Number:
AC52-07NA27344
Resource Relation:
Patent File Date: 2016 Oct 21
Research Org:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING