Title: Secure true random number generation using 1.5-T transistor flash memory

Abstract

This disclosure relates generally to physically unclonable function (PUF) circuitry along with methods of generating numbers. In one embodiment, the PUF circuitry includes a memory, a memory control circuitry, and whitening circuitry. To reduce or eliminate the systematic bias from the array, whitening circuitry is configured to generate a random number comprising random number bits in response to the memory control circuit implementing at least one sequence of memory cycles on the array of the memory cells in the memory. The whitening circuitry is configured to provide the random number bits of the random number based on the variable bit states stored by the array of the memory cells. On average the whitening circuitry is configured to provide approximately half of the random number bits in the first bit state and half of random number bits in a second bit state.

Inventors:

Clark, Lawrence T.; Adams, James; Holbert, Keith E.

Issue Date:

Tue Sep 18 00:00:00 EDT 2018

Research Org.:

Arizona Board of Regents on behalf of Arizona State University, Scottsdale, AZ (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1483257

Patent Number(s):

10078494

Application Number:

15/276,087

Assignee:

Arizona Board of Regents on behalf of Arizona State University (Scottsdale, AZ)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F7/588 - {Random number generators, i.e. based on natural stochastic processes}

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DOE Contract Number:  

NE0000679

Resource Type:

Patent

Resource Relation:

Patent File Date: 2016 Sep 26

Country of Publication:

United States

Language:

English

Subject:

97 MATHEMATICS AND COMPUTING