Low-inductance direct current power bus

Title: Low-inductance direct current power bus

A DC power bus having reduced parasitic inductance and higher tolerable operating temperature is disclosed. In example embodiments, a bus structure overlies a printed circuit board, and an array of capacitors is arranged on a surface of the printed circuit board distal the bus structure. The bus structure comprises an upper metal plate, a lower metal plate, and a dielectric film interposed between the upper and lower metal plates. The capacitors are connected in parallel between conductive planes of the printed circuit board. The upper and lower metal plates of the bus structure are connected to respective conductive planes of the printed circuit board.

Inventors:: Neely, Jason C.; Stewart, Joshua; Delhotal, Jarod James; Flicker, Jack David; Brennecka, Geoff L.

Issue Date:: 2018-09-25

OSTI Identifier:: 1482178

Assignee:: National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM) SNL

Patent Number(s):: 10,084,310

Application Number:: 15/426,844

Contract Number:: AC04-94AL85000

Resource Relation:: Patent File Date: 2017 Feb 07

Research Org:: Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)

Sponsoring Org:: USDOE

Country of Publication:: United States

Language:: English

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Works referenced in this record:

Electrostatic generator and motor
patent, November 1978

Wahlstrom, Sven E.
US Patent Document 4,126,822
URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect2=PTO1&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&d=PALL&RefSrch=yes&Query=PN%2F4126822

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