Low-inductance direct current power bus
Abstract
A DC power bus having reduced parasitic inductance and higher tolerable operating temperature is disclosed. In example embodiments, a bus structure overlies a printed circuit board, and an array of capacitors is arranged on a surface of the printed circuit board distal the bus structure. The bus structure comprises an upper metal plate, a lower metal plate, and a dielectric film interposed between the upper and lower metal plates. The capacitors are connected in parallel between conductive planes of the printed circuit board. The upper and lower metal plates of the bus structure are connected to respective conductive planes of the printed circuit board.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1482178
- Patent Number(s):
- 10084310
- Application Number:
- 15/426,844
- Assignee:
- National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
- Patent Classifications (CPCs):
-
B - PERFORMING OPERATIONS B60 - VEHICLES IN GENERAL B60R - VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- AC04-94AL85000
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2017 Feb 07
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Neely, Jason C., Stewart, Joshua, Delhotal, Jarod James, Flicker, Jack David, and Brennecka, Geoff L. Low-inductance direct current power bus. United States: N. p., 2018.
Web.
Neely, Jason C., Stewart, Joshua, Delhotal, Jarod James, Flicker, Jack David, & Brennecka, Geoff L. Low-inductance direct current power bus. United States.
Neely, Jason C., Stewart, Joshua, Delhotal, Jarod James, Flicker, Jack David, and Brennecka, Geoff L. Tue .
"Low-inductance direct current power bus". United States. https://www.osti.gov/servlets/purl/1482178.
@article{osti_1482178,
title = {Low-inductance direct current power bus},
author = {Neely, Jason C. and Stewart, Joshua and Delhotal, Jarod James and Flicker, Jack David and Brennecka, Geoff L.},
abstractNote = {A DC power bus having reduced parasitic inductance and higher tolerable operating temperature is disclosed. In example embodiments, a bus structure overlies a printed circuit board, and an array of capacitors is arranged on a surface of the printed circuit board distal the bus structure. The bus structure comprises an upper metal plate, a lower metal plate, and a dielectric film interposed between the upper and lower metal plates. The capacitors are connected in parallel between conductive planes of the printed circuit board. The upper and lower metal plates of the bus structure are connected to respective conductive planes of the printed circuit board.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {9}
}
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