Low-inductance direct current power bus
Abstract
A DC power bus having reduced parasitic inductance and higher tolerable operating temperature is disclosed. In example embodiments, a bus structure overlies a printed circuit board, and an array of capacitors is arranged on a surface of the printed circuit board distal the bus structure. The bus structure comprises an upper metal plate, a lower metal plate, and a dielectric film interposed between the upper and lower metal plates. The capacitors are connected in parallel between conductive planes of the printed circuit board. The upper and lower metal plates of the bus structure are connected to respective conductive planes of the printed circuit board.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1482178
- Patent Number(s):
- 10,084,310
- Application Number:
- 15/426,844
- Assignee:
- National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
- DOE Contract Number:
- AC04-94AL85000
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2017 Feb 07
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Neely, Jason C., Stewart, Joshua, Delhotal, Jarod James, Flicker, Jack David, and Brennecka, Geoff L. Low-inductance direct current power bus. United States: N. p., 2018.
Web.
Neely, Jason C., Stewart, Joshua, Delhotal, Jarod James, Flicker, Jack David, & Brennecka, Geoff L. Low-inductance direct current power bus. United States.
Neely, Jason C., Stewart, Joshua, Delhotal, Jarod James, Flicker, Jack David, and Brennecka, Geoff L. Tue .
"Low-inductance direct current power bus". United States. https://www.osti.gov/servlets/purl/1482178.
@article{osti_1482178,
title = {Low-inductance direct current power bus},
author = {Neely, Jason C. and Stewart, Joshua and Delhotal, Jarod James and Flicker, Jack David and Brennecka, Geoff L.},
abstractNote = {A DC power bus having reduced parasitic inductance and higher tolerable operating temperature is disclosed. In example embodiments, a bus structure overlies a printed circuit board, and an array of capacitors is arranged on a surface of the printed circuit board distal the bus structure. The bus structure comprises an upper metal plate, a lower metal plate, and a dielectric film interposed between the upper and lower metal plates. The capacitors are connected in parallel between conductive planes of the printed circuit board. The upper and lower metal plates of the bus structure are connected to respective conductive planes of the printed circuit board.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {9}
}
Save to My Library
You must Sign In or Create an Account in order to save documents to your library.
Works referenced in this record:
Electrostatic generator and motor
patent, November 1978
- Wahlstrom, Sven E.
- US Patent Document 4,126,822
Capacitive chip carrier and multilayer ceramic capacitors
patent, September 1982
- Bajorek, Christopher; Chance, Dudley; Ho, Chung
- US Patent Document 4,349,862
High value surface mounted capacitor
patent, February 1985
- Shioleno, Lewis
- US Patent Document 4,499,524
Multilayer through type capacitor array
patent, December 1996
- Fujishiro, Yoshikazu; Ishigaki, Takaya; Harada, Hiraku
- US Patent Document 5,590,016
Multi-layer ceramic substrate decoupling
patent, October 1999
- Blasi, Charles; Das, Gobinda; Motika, Franco
- US Patent Document 5,973,928
High power switching module
patent, March 2002
- Rinehart, Lawrence; Sankaran, Venkateswara; Miller, John
- US Patent Document 6,359,331
Semiconductor integrated circuit having at least one of a power supply plane and ground plane divided into parts insulated from one another
patent, August 2005
- Kinoshita, Yasushi
- US Patent Document 6,924,562
Light-emitting device, print head and image forming apparatus
patent, January 2013
- Okazaki, Sachiya
- US Patent Document 8,345,074
Power conversion device
patent, August 2016
- Koyano, Hironori; Nakamura, Takamasa; Saito, Masao
- US Patent Document 9,425,701
Power conversion apparatus with induction control
patent, September 2016
- Mori, Keisuke
- US Patent Document 9,444,359
Status quo and future prospects for metallized polypropylene energy storage capacitors
journal, October 2002
- Rabuffi, M.; Picci, G.
- IEEE Transactions on Plasma Science, Vol. 30, Issue 5
Miniature high voltage, high temperature component package development
conference, July 2016
- Rashkin, L. J.; Brocato, R. W.; Delhotal, J. J.
- 2016 IEEE International Power Modulator and High Voltage Conference (IPMHVC)
Modeling of busbars in high power neutral point clamped three-level inverters
journal, February 2008
- Yi, Rong; Zhao, Zhengming; Zhong, Yulin
- Tsinghua Science and Technology, Vol. 13, Issue 1, p. 91-97
Modeling of low inductive busbar connections
journal, January 1996
- Schanen, J. L.; Clavel, E.; Roudet, J.
- IEEE Industry Applications Magazine, Vol. 2, Issue 5, p. 39-43
Current Mode Control for Boost Converters With Constant Power Loads
journal, January 2012
- Li, Yushan; Vannorsdel, Kevin R.; Zirger, Art J.
- IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 59, Issue 1, p. 198-206
Modeling of parasitic inductive effects in power modules
conference, January 1997
- Falck, E.; Stoisiek, M.; Wachutka, G.
- Proceedings of 9th International Symposium on Power Semiconductor Devices and IC's