Title: Self-timed router with virtual channel control

Abstract

Systems, apparatuses, and methods for implementing an asynchronous router with virtual channel (VC) control. The asynchronous router may support multiple VCs for connections to other routers. The asynchronous router may include an interface unit on each switch boundary, with each interface unit including a data merge unit. The data merge unit may include a full detector unit for each VC, with the full detector unit counting the number of flits sent out on a respective VC and counting the number of credits released by the successor router. Whenever the successor router has no credits available, the full detector unit will assert the full signal to prevent any input requests from requesting to transmit over that particular VC. When the full signal is asserted, a timer unit may be activated to repeatedly check if any credits have been released in the successor router.

Inventors:

Jiang, Weiwei; Sadowski, Greg

Issue Date:

2018-09-11

Research Org.:

Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1477190

Patent Number(s):

10075383

Application Number:

15/085,783

Assignee:

Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION

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H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION

H04L47/527 - {Quantum based scheduling, e.g. credit or deficit based scheduling or token bank}

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DOE Contract Number:  

AC52-07NA27344

Resource Type:

Patent

Resource Relation:

Patent File Date: 2016 Mar 30

Country of Publication:

United States

Language:

English