Title: Collective network for computer structures

Abstract

A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.

Inventors:

Blumrich, Matthias A.; Coteus, Paul W.; Chen, Dong; Gara, Alan; Giampapa, Mark E.; Heidelberger, Philip; Hoenicke, Dirk; Takken, Todd E.; Steinmacher-Burow, Burkhard D.; Vranas, Pavlos M.

Issue Date:

2018-09-04

Research Org.:

International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1471566

Patent Number(s):

10069599

Application Number:

14/972,945

Assignee:

International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F11/08 - Error detection or correction by redundancy in data representation, e.g. by using checking codes
G06F11/1423 - {by reconfiguration of paths}
G06F9/46 - Multiprogramming arrangements

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING

H03M13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION

H04L1/0061 - {Error detection codes}
H04L1/08 - by repeating transmission, e.g. Verdan system {
H04L1/1607 - {Details of the supervisory signal}
H04L1/1867 - {Arrangements specific to the transmitter end}
H04L2001/0093 - {Point-to-multipoint}
H04L2001/0097 - {Relays}

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DOE Contract Number:  

B517552

Resource Type:

Patent

Resource Relation:

Patent File Date: 2015 Dec 17

Country of Publication:

United States

Language:

English