Light-weight cache coherence for data processors with limited data sharing
Abstract
A data processing system includes a plurality of processors, local memories associated with a corresponding processor, and at least one inter-processor link. In response to a first processor performing a load or store operation on an address of a corresponding local memory that is not currently in the local cache, a local cache allocates a first cache line and encodes a local state with the first cache line. In response to a load operation from an address of a remote memory that is not currently in the local cache, the local cache allocates a second cache line and encodes a remote state with the second cache line. The first processor performs subsequent loads and stores on the first cache line in the local cache in response to the local state, and subsequent loads from the second cache line in the local cache in response to the remote state.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1469175
- Patent Number(s):
- 10042762
- Application Number:
- 15/264,804
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC52-07NA27344
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2016 Sep 14
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Jayasena, Nuwan, and Boyer, Michael. Light-weight cache coherence for data processors with limited data sharing. United States: N. p., 2018.
Web.
Jayasena, Nuwan, & Boyer, Michael. Light-weight cache coherence for data processors with limited data sharing. United States.
Jayasena, Nuwan, and Boyer, Michael. Tue .
"Light-weight cache coherence for data processors with limited data sharing". United States. https://www.osti.gov/servlets/purl/1469175.
@article{osti_1469175,
title = {Light-weight cache coherence for data processors with limited data sharing},
author = {Jayasena, Nuwan and Boyer, Michael},
abstractNote = {A data processing system includes a plurality of processors, local memories associated with a corresponding processor, and at least one inter-processor link. In response to a first processor performing a load or store operation on an address of a corresponding local memory that is not currently in the local cache, a local cache allocates a first cache line and encodes a local state with the first cache line. In response to a load operation from an address of a remote memory that is not currently in the local cache, the local cache allocates a second cache line and encodes a remote state with the second cache line. The first processor performs subsequent loads and stores on the first cache line in the local cache in response to the local state, and subsequent loads from the second cache line in the local cache in response to the remote state.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {8}
}
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Works referenced in this record:
Active Memory Cube: A processing-in-memory architecture for exascale systems
journal, March 2015
- Nair, R.; Antao, S. F.; Bertolli, C.
- IBM Journal of Research and Development, Vol. 59, Issue 2/3, p. 17:1-17:14
QuickRelease: A throughput-oriented approach to release consistency on GPUs
conference, February 2014
- Hechtman, Blake A.; Che, Shuai; Hower, Derek R.
- 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
Memory management for a symmetric multiprocessor computer system
patent-application, November 2004
- Blake, Michael A.; Ford, Carl B.; Mak, Pak-Kin
- US Patent Application 10/436491; 20040230750
Method and apparatus for reducing overhead in a data processing system with a cache
patent-application, April 2004
- Conway, Patrick
- US Patent Application 10/261642; 20040064651
Assisted Coherent Shared Memory
patent-application, July 2015
- Das Sharma, Debendra; Kumar, Mohan J.; Fleischer, Balin T.
- US Patent Application 14/142726; 20150186215
Hybrid Input/Output Write Operations
patent-application, April 2015
- Hum, Herbert; Joshi, Chandra; Pal, Rahul
- US Patent Application 13/997426; 20150113221
Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors
conference, January 1995
- Lebeck, Alvin R.; Wood, David A.
- ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture, p. 48-59
Method and apparatus for injecting write data into a cache
patent, December 2006
- Hughes, William; Conway, Patrick
- US Patent Document 7,155,572
Two-stage request protocol for accessing remote memory data in a NUMA data processing system
patent, September 2003
- Arimilli, Ravi; Dodson, John; Fields, James
- US Patent Document 6,615,322
Methods and apparatus for providing cache state information
patent-application, November 2004
- Glasco, David Brian
- US Patent Application 10/442845; 20040236912
Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas
patent, July 1998
- Sukegawa, Naonobu; Tarui, Tshiaki; Fujii, Hiroaki
- US Patent Document 5,778,429
The directory-based cache coherence protocol for the DASH multiprocessor
journal, May 1990
- Lenoski, Daniel; Laudon, James; Gharachorloo, Kourosh
- ACM SIGARCH Computer Architecture News, Vol. 18, Issue 3, p. 148-159
Caching mechanism for remote read-only data in a cache coherent non-uniform memory access (CCNUMA) architecture
patent, July 2004
- Conway, Patrick; Nakagawa, Yukihiro; Jiang, Jung Rung
- US Patent Document 6,766,360
Cache coherence for GPU architectures
conference, February 2013
- Singh, I.; Shriraman, A.; Fung, W. W. L.
- 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology
journal, August 2009
- Kurita, Y.; Matsui, S.; Takahashi, N.
- IEEE Transactions on Advanced Packaging, Vol. 32, Issue 3, p. 657-665
Method and apparatus for a global cache directory in a storage cluster
patent-application, February 2003
- Chiu, Lawrence Yium-chee; Sun Hsu, Windsor Wee; Young, Honesty Cheng
- US Patent Application 09/851452; 20030028819
Hybrid Cache Coherence Using Fine-Grained Hardware Message Passing
patent-application, April 2009
- O'Krafka, Brian W.; Koka, Pranay; Kroeger, Robert J.
- US Patent Application 11/864507; 20090089511