Light-weight cache coherence for data processors with limited data sharing
Abstract
A data processing system includes a plurality of processors, local memories associated with a corresponding processor, and at least one inter-processor link. In response to a first processor performing a load or store operation on an address of a corresponding local memory that is not currently in the local cache, a local cache allocates a first cache line and encodes a local state with the first cache line. In response to a load operation from an address of a remote memory that is not currently in the local cache, the local cache allocates a second cache line and encodes a remote state with the second cache line. The first processor performs subsequent loads and stores on the first cache line in the local cache in response to the local state, and subsequent loads from the second cache line in the local cache in response to the remote state.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1469175
- Patent Number(s):
- 10,042,762
- Application Number:
- 15/264,804
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- DOE Contract Number:
- AC52-07NA27344
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2016 Sep 14
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Jayasena, Nuwan, and Boyer, Michael. Light-weight cache coherence for data processors with limited data sharing. United States: N. p., 2018.
Web.
Jayasena, Nuwan, & Boyer, Michael. Light-weight cache coherence for data processors with limited data sharing. United States.
Jayasena, Nuwan, and Boyer, Michael. Tue .
"Light-weight cache coherence for data processors with limited data sharing". United States. https://www.osti.gov/servlets/purl/1469175.
@article{osti_1469175,
title = {Light-weight cache coherence for data processors with limited data sharing},
author = {Jayasena, Nuwan and Boyer, Michael},
abstractNote = {A data processing system includes a plurality of processors, local memories associated with a corresponding processor, and at least one inter-processor link. In response to a first processor performing a load or store operation on an address of a corresponding local memory that is not currently in the local cache, a local cache allocates a first cache line and encodes a local state with the first cache line. In response to a load operation from an address of a remote memory that is not currently in the local cache, the local cache allocates a second cache line and encodes a remote state with the second cache line. The first processor performs subsequent loads and stores on the first cache line in the local cache in response to the local state, and subsequent loads from the second cache line in the local cache in response to the remote state.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {8}
}
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