Compensating for parasitic voltage drops in circuit arrays
Abstract
Various technologies for improving uniformity of operation of elements in an array circuit are described herein. In an exemplary embodiment, a plurality of resistive elements are incorporated into an array circuit such that voltages developed across any two elements is substantially the same when an equal voltage is applied to energize the elements. In a crossbar array circuit that comprises a plurality of elements arranged in rows and columns, the resistance of each of the resistive elements is based upon a row or column to which the resistive element is connected.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1469143
- Patent Number(s):
- 10043855
- Application Number:
- 15/841,670
- Assignee:
- National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
- Patent Classifications (CPCs):
-
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- NA0003525
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2017 Dec 14
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 42 ENGINEERING
Citation Formats
Agarwal, Sapan, and Marinella, Matthew. Compensating for parasitic voltage drops in circuit arrays. United States: N. p., 2018.
Web.
Agarwal, Sapan, & Marinella, Matthew. Compensating for parasitic voltage drops in circuit arrays. United States.
Agarwal, Sapan, and Marinella, Matthew. Tue .
"Compensating for parasitic voltage drops in circuit arrays". United States. https://www.osti.gov/servlets/purl/1469143.
@article{osti_1469143,
title = {Compensating for parasitic voltage drops in circuit arrays},
author = {Agarwal, Sapan and Marinella, Matthew},
abstractNote = {Various technologies for improving uniformity of operation of elements in an array circuit are described herein. In an exemplary embodiment, a plurality of resistive elements are incorporated into an array circuit such that voltages developed across any two elements is substantially the same when an equal voltage is applied to energize the elements. In a crossbar array circuit that comprises a plurality of elements arranged in rows and columns, the resistance of each of the resistive elements is based upon a row or column to which the resistive element is connected.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {8}
}
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Works referenced in this record:
High density resistor array
patent, October 1988
- Noel, Donald N.; Wolfe, Glenn
- US Patent Document 4,777,467
Balanced and bi-directional bit line paths for memory arrays with programmable memory cells
patent, March 2009
- De Brosse, John K.; Lamorey, Mark C. H.
- US Patent Document 7,505,348
Display apparatus, and image signal processing apparatus and drive control apparatus for the same
patent-application, July 2003
- Abe, Naoto; Inamura, Kohei; Sagano, Osamu
- US Patent Application 10/300538; 20030122759
Driving apparatus, driver circuit, and image display apparatus
patent-application, January 2004
- Shino, Kenji; Aoki, Tadashi; Murayama, Kazuhiko
- US Patent Application 10/460231; 20040001039
Drive circuit
patent-application, November 2004
- Shino, Kenji; Noine, Yasukazu
- US Patent Application 10/766817; 20040217950
Resistance balance circuit
patent-application, September 2008
- Huang, Tien-Fu; Hu, Kuo-Chang; Hua, Shih-Hao
- US Patent Application 11/976561; 20080211750
Rechargeable Battery Array
patent-application, March 2009
- Choi, Kai-Wai Alexander; Chan, Sheung Wa
- US Patent Application 11/861872; 20090079390
Memory Device with Asymmetrical Bit Cell Arrays and Balanced Resistance and Capacitance
patent-application, May 2012
- Chang, Feng-Ming; Yang, Chang-Ta; Huang, Huai-Ying
- US Patent Application 12/946136; 20120120703
Display Device
patent-application, June 2013
- Ebisuno, Kouhei; Kato, Toshiyuki; Segawa, Yasuo
- US Patent Application 13/768334; 20130162622