Smart memory buffers

Yoon, Doe Hyun; Muralimanohar, Naveen; Chang, Jichuan; Ranganathan, Parthasarathy

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A - human necessities
A01 - agriculture
A21 - baking
A22 - butchering
A23 - foods or foodstuffs
A24 - tobacco
A41 - wearing apparel
A42 - headwear
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A44 - haberdashery
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A47 - furniture
A61 - medical or veterinary science
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A99 - subject matter not otherwise provided for in this section
B - performing operations
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B03 - separation of solid materials using liquids or using pneumatic tables or jigs
B04 - centrifugal apparatus or machines for carrying-out physical or chemical processes
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B21 - mechanical metal-working without essentially removing material
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B60 - vehicles in general
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B62 - land vehicles for travelling otherwise than on rails
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B67 - opening, closing {or cleaning} bottles, jars or similar containers
B68 - saddlery
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C01 - inorganic chemistry
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D01 - natural or man-made threads or fibres
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Title: Smart memory buffers

Abstract

An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.

Inventors:: Yoon, Doe Hyun; Muralimanohar, Naveen; Chang, Jichuan; Ranganathan, Parthasarathy

Issue Date:: 2018-07-10

Research Org.:: Hewlett Packard Enterprise Development LP, Houston, TX (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1462696

Patent Number(s):: 10019176

Application Number:: 14/417,220

Assignee:: Hewlett Packard Enterprise Development LP (Houston, TX)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/108 - {Parity data distribution in semiconductor storages, e.g. in SSD}
G06F2211/1054 - Parity-fast hardware, i.e. dedicated fast hardware for RAID systems with parity
G06F2211/1066 - Parity-small-writes, i.e. improved small or partial write techniques in RAID systems
G06F3/0619 - {in relation to data integrity, e.g. data losses, bit errors}
G06F3/065 - {Replication mechanisms}
G06F3/0655 - {Vertical data movement, i.e. input-output transfer
G06F3/0656 - {Data buffering arrangements}
G06F3/0665 - {at area level, e.g. provisioning of virtual or logical volumes}
G06F3/0688 - {Non-volatile semiconductor memory arrays}
G06F3/0689 - {Disk arrays, e.g. RAID, JBOD}

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DOE Contract Number:: SC0005026

Resource Type:: Patent

Resource Relation:: Patent File Date: 2012 Oct 30

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Yoon, Doe Hyun, Muralimanohar, Naveen, Chang, Jichuan, and Ranganathan, Parthasarathy. Smart memory buffers.  United States: N. p., 2018. 
        Web.

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                    Yoon, Doe Hyun, Muralimanohar, Naveen, Chang, Jichuan, & Ranganathan, Parthasarathy. Smart memory buffers.  United States.

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                    Yoon, Doe Hyun, Muralimanohar, Naveen, Chang, Jichuan, and Ranganathan, Parthasarathy. Tue .  
        "Smart memory buffers".  United States.  https://www.osti.gov/servlets/purl/1462696.

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@article{osti_1462696,

  title        = {Smart memory buffers},

  author       = {Yoon, Doe Hyun and Muralimanohar, Naveen and Chang, Jichuan and Ranganathan, Parthasarathy},

  abstractNote = {An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2018},

  month        = {7}

}

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Works referenced in this record:

Synchronization method for loosely coupled arrays of redundant disk drives
patent, January 1996

Mendelsohn, Noah R.
US Patent Document 5,488,731
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5488731

Data storage device matrix architecture
patent, August 1996

DuLac, Keith B.
US Patent Document 5,550,986
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5550986

XOR controller for a storage subsystem
patent, January 1997

Winkler, Jeffrey L.; Wilcox, Jeffrey
US Patent Document 5,594,862
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5594862

Method for performing a RAID stripe write operation using a drive XOR command set
patent, April 1998

DeKoning, Rodney A.
US Patent Document 5,742,752
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5742752

Method and system for detecting fraudulent data update
patent, November 1999

Akatsu, Masaharu
US Patent Document 5,982,890
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5982890

Methods and arrangements for hybrid data storage
patent, September 2009

Daniels, Scott Leonard
US Patent Document 7,584,335
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7584335

Hybrid memory device with single interface
patent, May 2010

Panabaker, Ruston; Creasey, Jack
US Patent Document 7,716,411
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7716411

Memory controller using time-staggered lockstep sub-channels with buffered memory
patent, November 2011

Christenson, Bruce A.; Agarwal, Rajat
US Patent Document 8,060,692
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8060692

Securely and Autonomously Synchronizing Data in a Distributed Computing Environment
patent-application, July 2002

Norris, Jeffrey S.; Backes, Paul G.
US Patent Application 09/746550; 20020095568
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20020095568

Memory System and Method of Using Same
patent-application, February 2003

Walton, John K.; Bermingham, Michael; MacLellan, Christopher S.
US Patent Application 09/927042; 20030033572
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20030033572

Data File Migration from a Mirrored Raid to a Non-Mirrored XOR-Based Raid without Rewriting the Data
patent-application, October 2003

Holland, Mark C.; Welch, Brent B.
US Patent Application 10/109998; 20030188097
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20030188097

Method of Managing a Solid State Drive, Associated Systems and Implementations
patent-application, April 2010

Heo, Jin Gyu; Lee, Donggi; Hwang, Seongsik
US Patent Application 12/585935; 20100082890
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20100082890

Hybrid Volatile and Non-Volatile Memory Device
patent-application, May 2010

Best, Scott C.
US Patent Application 12/596115; 20100110748
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20100110748

Systems, Methods, and Apparatuses for Hybrid Memory
patent-application, June 2011

Casper, Bryan; Mooney, Randy; Dunning, Dave
US Patent Application 12/655590; 20110161748
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20110161748

Redundant Array of Independent Storage
patent-application, August 2011

Popovski, Vladimir; Nahum, Nelson; Pinson, Jeremy M.
US Patent Application 12/959622; 20110202721
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20110202721

Read-Modify-Write Protocol for Maintaining Parity Coherency in a Write-Back Distributed Redundancy Data Storage System
patent-application, August 2011

Hafner, James L.; Pandey, Prashant; Thakur, Tarun
US Patent Application 12/710123; 20110208995
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20110208995

Storage Subsystem
patent-application, September 2011

Kitahara, Jun; Takada, Masanori; Sugimoto, Sadahiro
US Patent Application 12/526666; 20110238885
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20110238885

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Similar Records

Title: Smart memory buffers

Abstract

Citation Formats

Synchronization method for loosely coupled arrays of redundant disk drives patent, January 1996

Data storage device matrix architecture patent, August 1996

XOR controller for a storage subsystem patent, January 1997

Method for performing a RAID stripe write operation using a drive XOR command set patent, April 1998

Method and system for detecting fraudulent data update patent, November 1999

Methods and arrangements for hybrid data storage patent, September 2009

Hybrid memory device with single interface patent, May 2010

Memory controller using time-staggered lockstep sub-channels with buffered memory patent, November 2011

Securely and Autonomously Synchronizing Data in a Distributed Computing Environment patent-application, July 2002

Memory System and Method of Using Same patent-application, February 2003

Data File Migration from a Mirrored Raid to a Non-Mirrored XOR-Based Raid without Rewriting the Data patent-application, October 2003

Method of Managing a Solid State Drive, Associated Systems and Implementations patent-application, April 2010

Hybrid Volatile and Non-Volatile Memory Device patent-application, May 2010

Systems, Methods, and Apparatuses for Hybrid Memory patent-application, June 2011

Redundant Array of Independent Storage patent-application, August 2011

Read-Modify-Write Protocol for Maintaining Parity Coherency in a Write-Back Distributed Redundancy Data Storage System patent-application, August 2011

Storage Subsystem patent-application, September 2011

Synchronization method for loosely coupled arrays of redundant disk drives
patent, January 1996

Data storage device matrix architecture
patent, August 1996

XOR controller for a storage subsystem
patent, January 1997

Method for performing a RAID stripe write operation using a drive XOR command set
patent, April 1998

Method and system for detecting fraudulent data update
patent, November 1999

Methods and arrangements for hybrid data storage
patent, September 2009

Hybrid memory device with single interface
patent, May 2010

Memory controller using time-staggered lockstep sub-channels with buffered memory
patent, November 2011

Securely and Autonomously Synchronizing Data in a Distributed Computing Environment
patent-application, July 2002

Memory System and Method of Using Same
patent-application, February 2003

Data File Migration from a Mirrored Raid to a Non-Mirrored XOR-Based Raid without Rewriting the Data
patent-application, October 2003

Method of Managing a Solid State Drive, Associated Systems and Implementations
patent-application, April 2010

Hybrid Volatile and Non-Volatile Memory Device
patent-application, May 2010

Systems, Methods, and Apparatuses for Hybrid Memory
patent-application, June 2011

Redundant Array of Independent Storage
patent-application, August 2011

Read-Modify-Write Protocol for Maintaining Parity Coherency in a Write-Back Distributed Redundancy Data Storage System
patent-application, August 2011

Storage Subsystem
patent-application, September 2011