Global to push GA events into
skip to main content

Title: Architecture for on-die interconnect

In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.
Inventors:
; ; ;
Issue Date:
OSTI Identifier:
1457407
Assignee:
Intel Corporation (Santa Clara, CA) NNSA
Patent Number(s):
9,998,401
Application Number:
15/042,402
Contract Number:
B600738
Resource Relation:
Patent File Date: 2016 Feb 12
Research Org:
Intel Corporation, Santa Clara, CA (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English

Similar records in DOepatents and OSTI.GOV collections: