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Title: Architecture for on-die interconnect

Abstract

In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.

Inventors:
; ; ;
Issue Date:
Research Org.:
Intel Corporation, Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1457407
Patent Number(s):
9,998,401
Application Number:
15/042,402
Assignee:
Intel Corporation (Santa Clara, CA)
DOE Contract Number:  
B600738
Resource Type:
Patent
Resource Relation:
Patent File Date: 2016 Feb 12
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING

Citation Formats

Khare, Surhud, More, Ankit, Somasekhar, Dinesh, and Dunning, David S. Architecture for on-die interconnect. United States: N. p., 2018. Web.
Khare, Surhud, More, Ankit, Somasekhar, Dinesh, & Dunning, David S. Architecture for on-die interconnect. United States.
Khare, Surhud, More, Ankit, Somasekhar, Dinesh, and Dunning, David S. Tue . "Architecture for on-die interconnect". United States. https://www.osti.gov/servlets/purl/1457407.
@article{osti_1457407,
title = {Architecture for on-die interconnect},
author = {Khare, Surhud and More, Ankit and Somasekhar, Dinesh and Dunning, David S.},
abstractNote = {In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {6}
}

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Works referenced in this record:

Express Cube Topologies for on-Chip Interconnects
conference, February 2009

  • Grot, Boris; Hestness, Joel; Keckler, Stephen W.
  • 2009 IEEE 15th International Symposium on High Performance Computer Architecture
  • DOI: 10.1109/HPCA.2009.4798251

Cost-Efficient Dragonfly Topology for Large-Scale Systems
conference, January 2009

  • Kim, John; Dally, William J.; Scott, Steve
  • Optical Fiber Communication Conference
  • DOI: 10.1364/OFC.2009.OTuI2