Architecture for on-die interconnect
Abstract
In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.
- Inventors:
- Issue Date:
- Research Org.:
- Intel Corporation, Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1457407
- Patent Number(s):
- 9998401
- Application Number:
- 15/042,402
- Assignee:
- Intel Corporation (Santa Clara, CA)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- DOE Contract Number:
- B600738
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2016 Feb 12
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 42 ENGINEERING
Citation Formats
Khare, Surhud, More, Ankit, Somasekhar, Dinesh, and Dunning, David S. Architecture for on-die interconnect. United States: N. p., 2018.
Web.
Khare, Surhud, More, Ankit, Somasekhar, Dinesh, & Dunning, David S. Architecture for on-die interconnect. United States.
Khare, Surhud, More, Ankit, Somasekhar, Dinesh, and Dunning, David S. Tue .
"Architecture for on-die interconnect". United States. https://www.osti.gov/servlets/purl/1457407.
@article{osti_1457407,
title = {Architecture for on-die interconnect},
author = {Khare, Surhud and More, Ankit and Somasekhar, Dinesh and Dunning, David S.},
abstractNote = {In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {6}
}
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Works referenced in this record:
Multi-chip package and interposer with signal line compression
patent, October 2015
- Partsch, Torsten
- US Patent Document 9,153,508
Interconnect to Communicate Information Uni-Directionally
patent-application, June 2014
- Conrad, Shaun M.; Knolla, William; Moran, Douglas R.
- US Patent Application 13/727052; 20140181352
Scaleable low-latency switch for usage in an interconnect structure
patent, September 2001
- Hesse, John
- US Patent Document 6,289,021
Cost-Efficient Dragonfly Topology for Large-Scale Systems
conference, January 2009
- Kim, John; Dally, William J.; Scott, Steve
- Optical Fiber Communication Conference
Network device configured to generate empty route for limiting number of withdrawal messages
patent, August 2016
- Kotalwar, Jayant
- US Patent Document 9,432,280
Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity
patent, February 2004
- Borst, Christopher Lyle; Tsao, Alwin; Strong, Bobby D.
- US Patent Document 6,693,357
Method and Device for Scheduling Unicast and Multicast Traffic in an Interconnecting Fabric
patent-application, September 2008
- Minkenberg, Cyriel; Abel, Francois G.; Schiattarella, Enrice
- US Patent Application 12/047146; 20080219269
Integration of Processor and Input/Output Hub
patent-application, December 2011
- Looi, Lily Pao; Jourdan, Stephan J.; Bikgin, Selim
- US Patent Application 12/791836; 20110296216
Die-Stacked Device With Partitioned Multi-Hop Network
patent-application, June 2014
- Thottethodi, Mithuna; Loh, Gabriel
- US Patent Application 13/726142; 20140177626
Inter-Processor Communication Channel Including Power-Down Functionality
patent-application, April 2010
- Millet, Timothy; Mathew, Binu K.; Schell, Stephan Vincent
- US Patent Application 12/238700; 20100083026
Semiconductor device
patent, April 2014
- Hirano, Hiroshige; Ota, Yukitoshi
- US Patent Document 8,710,667
Cost-Efficient Dragonfly Topology for Large-Scale Systems
journal, January 2009
- Kim, John; Dally, William; Scott, Steve
- IEEE Micro, Vol. 29, Issue 1
Data structure-less distributed fabric multicast
patent, October 2014
- Baban, Alex; Frailong, Jean-Marc; Kompella, Kireeti
- US Patent Document 8,873,554
Express Cube Topologies for on-Chip Interconnects
conference, February 2009
- Grot, Boris; Hestness, Joel; Keckler, Stephen W.
- 2009 IEEE 15th International Symposium on High Performance Computer Architecture