Combined guaranteed throughput and best effort network-on-chip

Chen, Gregory K.; Anders, Mark A.; Kaul, Himanshu; Krishnamurthy, Ram K.; Stillmaker, Aaron T.

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A - human necessities
A01 - agriculture
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Title: Combined guaranteed throughput and best effort network-on-chip

Abstract

A first packet-switched reservation request is received. Data associated with the first packet-switched reservation request is communicated through a first circuit-switched channel according to a best effort communication scheme. A second packet-switched reservation request is received. Data associated with the second packet-switched reservation request is communicated through a second circuit-switched channel according to a guaranteed throughput communication scheme.

Inventors:: Chen, Gregory K.; Anders, Mark A.; Kaul, Himanshu; Krishnamurthy, Ram K.; Stillmaker, Aaron T.

Issue Date:: 2018-05-22

Research Org.:: Intel Corporation, Santa Clara, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1440780

Patent Number(s):: 9979668

Application Number:: 14/579,303

Assignee:: Intel Corporation (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F15/7825 - {Globally asynchronous, locally synchronous, e.g. network on chip}

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
H04L12/6402 - {Hybrid switching fabrics}
H04L47/625 - {Other criteria for service slot or service order}
H04L47/72 - {Reservation actions}
H04L49/30 - {Peripheral units, e.g. input or output ports}

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
Y02D10/00 - Energy efficient computing

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DOE Contract Number:: 6600738

Resource Type:: Patent

Resource Relation:: Patent File Date: 2014 Dec 22

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Chen, Gregory K., Anders, Mark A., Kaul, Himanshu, Krishnamurthy, Ram K., and Stillmaker, Aaron T. Combined guaranteed throughput and best effort network-on-chip.  United States: N. p., 2018. 
        Web.

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                    Chen, Gregory K., Anders, Mark A., Kaul, Himanshu, Krishnamurthy, Ram K., & Stillmaker, Aaron T. Combined guaranteed throughput and best effort network-on-chip.  United States.

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                    Chen, Gregory K., Anders, Mark A., Kaul, Himanshu, Krishnamurthy, Ram K., and Stillmaker, Aaron T. Tue .  
        "Combined guaranteed throughput and best effort network-on-chip".  United States.  https://www.osti.gov/servlets/purl/1440780.

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@article{osti_1440780,

  title        = {Combined guaranteed throughput and best effort network-on-chip},

  author       = {Chen, Gregory K. and Anders, Mark A. and Kaul, Himanshu and Krishnamurthy, Ram K. and Stillmaker, Aaron T.},

  abstractNote = {A first packet-switched reservation request is received. Data associated with the first packet-switched reservation request is communicated through a first circuit-switched channel according to a best effort communication scheme. A second packet-switched reservation request is received. Data associated with the second packet-switched reservation request is communicated through a second circuit-switched channel according to a guaranteed throughput communication scheme.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2018},

  month        = {5}

}

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Works referenced in this record:

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Similar Records

Title: Combined guaranteed throughput and best effort network-on-chip

Abstract

Citation Formats

Multi-core processor and method of communicating across a die patent, October 2012

Using criticality information to route cache coherency communications patent-application, December 2009

16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS conference, February 2014

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Aelite: A flit-synchronous Network on Chip with composable and predictable services conference, April 2009

Statistical Approach to Networks-on-Chip journal, June 2010

Priority-Based Routing patent-application, July 2015

A 1.2 TB/s on-chip ring interconnect for 45nm 8-core enterprise Xeon® processor conference, February 2010

Architecture and Method for Hybrid Circuit-Switched and Packet-Switched Router patent-application, March 2015

A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS conference, February 2010

Quality-of-service and error control techniques for network-on-chip architectures conference, January 2004

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A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS conference, September 2008

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patent, October 2012

Using criticality information to route cache coherency communications
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conference, February 2014

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patent-application, August 2008

Aelite: A flit-synchronous Network on Chip with composable and predictable services
conference, April 2009

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A 1.2 TB/s on-chip ring interconnect for 45nm 8-core enterprise Xeon® processor
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Architecture and Method for Hybrid Circuit-Switched and Packet-Switched Router
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A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS
conference, February 2010

Quality-of-service and error control techniques for network-on-chip architectures
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