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Title: Multi-petascale highly efficient parallel supercomputer

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
Inventors:
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Issue Date:
OSTI Identifier:
1440757
Assignee:
GLOBALFOUNDRIES INC. (Grand Cayman, KY) OSTI
Patent Number(s):
9,971,713
Application Number:
14/701,371
Contract Number:
B554331
Resource Relation:
Patent File Date: 2015 Apr 30
Research Org:
GLOBALFOUNDRIES INC., Grand Cayman, KY (Cayman Islands)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING