IC layout adjustment method and tool for improving dielectric reliability at interconnects
Abstract
Method for adjusting a layout used in making an integrated circuit includes one or more interconnects in the layout that are susceptible to dielectric breakdown are selected. One or more selected interconnects are adjusted to increase via to wire spacing with respect to at least one via and one wire of the one or more selected interconnects. Preferably, the selecting analyzes signal patterns of interconnects, and estimates the stress ratio based on state probability of routed signal nets in the layout. An annotated layout is provided that describes distances by which one or more via or wire segment edges are to be shifted. Adjustments can include thinning and shifting of wire segments, and rotation of vias.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1429086
- Patent Number(s):
- 9922161
- Application Number:
- 14/767,458
- Assignee:
- The Regents of the University of California (Oakland, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02P - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- DOE Contract Number:
- AC04-94AL8500
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2014 Feb 20
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 42 ENGINEERING
Citation Formats
Kahng, Andrew B., and Chan, Tuck Boon. IC layout adjustment method and tool for improving dielectric reliability at interconnects. United States: N. p., 2018.
Web.
Kahng, Andrew B., & Chan, Tuck Boon. IC layout adjustment method and tool for improving dielectric reliability at interconnects. United States.
Kahng, Andrew B., and Chan, Tuck Boon. Tue .
"IC layout adjustment method and tool for improving dielectric reliability at interconnects". United States. https://www.osti.gov/servlets/purl/1429086.
@article{osti_1429086,
title = {IC layout adjustment method and tool for improving dielectric reliability at interconnects},
author = {Kahng, Andrew B. and Chan, Tuck Boon},
abstractNote = {Method for adjusting a layout used in making an integrated circuit includes one or more interconnects in the layout that are susceptible to dielectric breakdown are selected. One or more selected interconnects are adjusted to increase via to wire spacing with respect to at least one via and one wire of the one or more selected interconnects. Preferably, the selecting analyzes signal patterns of interconnects, and estimates the stress ratio based on state probability of routed signal nets in the layout. An annotated layout is provided that describes distances by which one or more via or wire segment edges are to be shifted. Adjustments can include thinning and shifting of wire segments, and rotation of vias.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {3}
}
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