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Title: Centrally managed unified shared virtual address space

Abstract

Systems, apparatuses, and methods for managing a unified shared virtual address space. A host may execute system software and manage a plurality of nodes coupled to the host. The host may send work tasks to the nodes, and for each node, the host may externally manage the node's view of the system's virtual address space. Each node may have a central processing unit (CPU) style memory management unit (MMU) with an internal translation lookaside buffer (TLB). In one embodiment, the host may be coupled to a given node via an input/output memory management unit (IOMMU) interface, where the IOMMU frontend interface shares the TLB with the given node's MMU. In another embodiment, the host may control the given node's view of virtual address space via memory-mapped control registers.

Inventors:
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1420778
Patent Number(s):
9,892,058
Application Number:
14/970,940
Assignee:
Advanced Micro Devices, Inc. (Sunnyvale, CA) LLNL
DOE Contract Number:  
AC52-07NA27344
Resource Type:
Patent
Resource Relation:
Patent File Date: 2015 Dec 16
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Wilkes, John. Centrally managed unified shared virtual address space. United States: N. p., 2018. Web.
Wilkes, John. Centrally managed unified shared virtual address space. United States.
Wilkes, John. Tue . "Centrally managed unified shared virtual address space". United States. https://www.osti.gov/servlets/purl/1420778.
@article{osti_1420778,
title = {Centrally managed unified shared virtual address space},
author = {Wilkes, John},
abstractNote = {Systems, apparatuses, and methods for managing a unified shared virtual address space. A host may execute system software and manage a plurality of nodes coupled to the host. The host may send work tasks to the nodes, and for each node, the host may externally manage the node's view of the system's virtual address space. Each node may have a central processing unit (CPU) style memory management unit (MMU) with an internal translation lookaside buffer (TLB). In one embodiment, the host may be coupled to a given node via an input/output memory management unit (IOMMU) interface, where the IOMMU frontend interface shares the TLB with the given node's MMU. In another embodiment, the host may control the given node's view of virtual address space via memory-mapped control registers.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {2}
}

Patent:

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