Unaligned instruction relocation

Bertolli, Carlo; O'Brien, John K.; Sallenave, Olivier H.; Sura, Zehra N.

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Title: Unaligned instruction relocation

Abstract

In one embodiment, a computer-implemented method includes receiving source code to be compiled into an executable file for an unaligned instruction set architecture (ISA). Aligned assembled code is generated, by a computer processor. The aligned assembled code complies with an aligned ISA and includes aligned processor code for a processor and aligned accelerator code for an accelerator. A first linking pass is performed on the aligned assembled code, including relocating a first relocation target in the aligned accelerator code that refers to a first object outside the aligned accelerator code. Unaligned assembled code is generated in accordance with the unaligned ISA and includes unaligned accelerator code for the accelerator and unaligned processor code for the processor. A second linking pass is performed on the unaligned assembled code, including relocating a second relocation target outside the unaligned accelerator code that refers to an object in the unaligned accelerator code.

Inventors:: Bertolli, Carlo; O'Brien, John K.; Sallenave, Olivier H.; Sura, Zehra N.

Issue Date:: 2018-01-23

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1417876

Patent Number(s):: 9875089

Application Number:: 14/744,047

Assignee:: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F8/445 - {Exploiting fine grain parallelism, i.e. parallelism at instruction level
G06F8/54 - Link editing before load time
G06F9/3001 - {Arithmetic instructions}
G06F9/3012 - {Organisation of register space, e.g. banked or distributed register file}

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DOE Contract Number:: B599858

Resource Type:: Patent

Resource Relation:: Patent File Date: 2015 Jun 19

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Bertolli, Carlo, O'Brien, John K., Sallenave, Olivier H., and Sura, Zehra N. Unaligned instruction relocation.  United States: N. p., 2018. 
        Web.

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                    Bertolli, Carlo, O'Brien, John K., Sallenave, Olivier H., & Sura, Zehra N. Unaligned instruction relocation.  United States.

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                    Bertolli, Carlo, O'Brien, John K., Sallenave, Olivier H., and Sura, Zehra N. Tue .  
        "Unaligned instruction relocation".  United States.  https://www.osti.gov/servlets/purl/1417876.

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@article{osti_1417876,

  title        = {Unaligned instruction relocation},

  author       = {Bertolli, Carlo and O'Brien, John K. and Sallenave, Olivier H. and Sura, Zehra N.},

  abstractNote = {In one embodiment, a computer-implemented method includes receiving source code to be compiled into an executable file for an unaligned instruction set architecture (ISA). Aligned assembled code is generated, by a computer processor. The aligned assembled code complies with an aligned ISA and includes aligned processor code for a processor and aligned accelerator code for an accelerator. A first linking pass is performed on the aligned assembled code, including relocating a first relocation target in the aligned accelerator code that refers to a first object outside the aligned accelerator code. Unaligned assembled code is generated in accordance with the unaligned ISA and includes unaligned accelerator code for the accelerator and unaligned processor code for the processor. A second linking pass is performed on the unaligned assembled code, including relocating a second relocation target outside the unaligned accelerator code that refers to an object in the unaligned accelerator code.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2018},

  month        = {1}

}

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Similar Records

Title: Unaligned instruction relocation

Abstract

Citation Formats

Relocatable file format and method and apparatus for creating and loading same patent, June 1998

Instruction compression and decompression system and method for a processor patent, October 1998

Assembler system and method for a geometry accelerator patent, March 1999

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Instruction to load data up to a specified memory boundary indicated by the instruction patent, July 2016

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System and software for matched aligned and unaligned storage instructions patent-application, August 2004

Multiple-thread processor for threaded software applications patent-application, January 2005

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Programming environment for heterogeneous processor resource integration patent-application, October 2008

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Processors, Methods, Systems, and Instructions to Generate Sequences of Integers in which Integers in Consecutive Positions Differ by a Constant Integer Stride and Where a Smallest Integer is Offset from Zero by an Integer Offset patent-application, October 2013

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Relocatable file format and method and apparatus for creating and loading same
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Instruction compression and decompression system and method for a processor
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Assembler system and method for a geometry accelerator
patent, March 1999

Object-code compatible representation of very long instruction word programs
patent, September 1999

Linker using relocation sequences
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Aligning load/store data with big/little endian determined rotation distance control
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Transforming non-contiguous instruction specifiers to contiguous instruction specifiers
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Rewriting symbol address initialization sequences
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Method, apparatus and article for generation of debugging information
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System and software for matched aligned and unaligned storage instructions
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Multiple-thread processor for threaded software applications
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System and method for simulating hardware interrupts
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Programming environment for heterogeneous processor resource integration
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Methods and Apparatus for Storage and Translation of Entropy Encoded Software Embedded within a Memory Hierarchy
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Processors, Methods, Systems, and Instructions to Generate Sequences of Integers in which Integers in Consecutive Positions Differ by a Constant Integer Stride and Where a Smallest Integer is Offset from Zero by an Integer Offset
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