Multithreading in vector processors
Abstract
In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1417324
- Patent Number(s):
- 9870340
- Application Number:
- 14/672,568
- Assignee:
- INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- B599858
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2015 Mar 30
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Evangelinos, Constantinos, Kim, Changhoan, and Nair, Ravi. Multithreading in vector processors. United States: N. p., 2018.
Web.
Evangelinos, Constantinos, Kim, Changhoan, & Nair, Ravi. Multithreading in vector processors. United States.
Evangelinos, Constantinos, Kim, Changhoan, and Nair, Ravi. Tue .
"Multithreading in vector processors". United States. https://www.osti.gov/servlets/purl/1417324.
@article{osti_1417324,
title = {Multithreading in vector processors},
author = {Evangelinos, Constantinos and Kim, Changhoan and Nair, Ravi},
abstractNote = {In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2018},
month = {1}
}
Works referenced in this record:
Processor for controlling tread switching
patent, January 2012
- Yokoi, Megumi; Ukai, Masaki
- US Patent Document 8,108,859
Data processing systems
patent-application, December 2014
- Nystad, Jorn; Engh-Halstvedt, Andreas
- US Patent Application 13/918664: 20140372731
Thread properties attribute vector based thread selection in multithreading processor
patent, June 2000
- Emer, Joel S.; Stamm, Rebecca L.; Fossum, Trggve
- US Patent Document 6,073,159
Multithreaded processor with multiple concurrent pipelines per thread
patent, November 2014
- Hokenek, Erdem; Moudgill, Mayan; Schulte, Michael J.
- US Patent Document 8,892,849
Multithreaded processor with efficient processing for convergence device applications
patent, November 2005
- Hokenek, Erdem; Moudgill, Mayan; Glossner, C. John
- US Patent Document 6,968,445
Processing Unit Incorporating Multirate Execution Unit
patent-application, July 2009
- Mejdrich, Eric Oliver; Muff, Adam James; Tubbs, Matthew Ray
- US Patent Application 11/972746: 20090182987
Thread-aware cache memory management
patent, December 2015
- O'Bleness, R. Frank; Jamil, Sujat; Hameenanttila, Tom
- US Patent Document 9,223,709
Enhanced load lookahead prefetch in single threaded mode for a simultaneous multithreaded microprocessor
patent-application, December 2008
- Le, Hung Q.; Nguyen, Dung Q.
- US Patent Application 11/763760: 20080313425
Digital data processing apparatus having multi-level register file
patent-application, December 2005
- Nunamaker, Nathan Samuel; Randolph, Jack Chris; Tsuchiya, Kenichi
- US Patent Application 10/875373; 20050289299
Effective use of a hardware barrier synchronization register for protocol synchronization
patent-application, March 2008
- Chaudhary, Piyush; Govindaraju, Rama K.; Kim, Chulho
- US Patent Application 11/534891: 20080077921
Interleaved multi-threaded vector processor
patent-application, November 2010
- Ahmed, Muhammad; Schaub, Marc; Rakib, Shlomo Selim
- US Patent Application 12/433826: 20100281234
Mechanisms for assuring quality of service for programs executing on a multithreaded processor
patent-application, March 2005
- Kissell, Kevin D.
- US Patent Application 10/684350: 20050050395
Multi-core multi-thread processor
patent-application, February 2005
- Olukotun, Kunle A.
- US Patent Application 10/855233; 20050044319
Method and apparatus for efficient utilization for prescient instruction prefetch
patent-application, March 2005
- Aamodt, Tor M.; Wang, Hong; Hammarlund, Per
- US Patent Application 10/658072; 20050055541
Performance study of a multithreaded superscalar microprocessor
conference, January 1996
- Gulati, M.; Bagherzadeh, N.
- Proceedings. Second International Symposium on High-Performance Computer Architecture
Vector register file
patent-application, February 2014
- Fleischer, Bruce M.; Fox, Thomas W.; Jacobson, Hans M.
- US Patent Application 13/570372: 20140047214