Title: Scalable polylithic on-package integratable apparatus and method

Abstract

Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

Inventors:

Khare, Surhud; Somasekhar, Dinesh; Borkar, Shekhar Y.

Issue Date:

Tue Dec 05 00:00:00 EST 2017

Research Org.:

Intel Corporation, Santa Clara, CA (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1411393

Patent Number(s):

9837391

Application Number:

14/967,231

Assignee:

Intel Corporation (Santa Clara, CA)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F1/12 - Synchronisation of different clock signals {provided by a plurality of clock generators}
G06F13/4022 - {using switching circuits, e.g. switching matrix, connection or expansion network

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

H01L21/78 - with subsequent division of the substrate into plural individual devices
H01L23/5221 - {Crossover interconnections}
H01L23/528 - {Geometry or} layout of the interconnection structure {
H01L23/53238 - {Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers}
H01L23/53295 - {Stacked insulating layers}
H01L23/5386 - {Geometry or layout of the interconnection structure}
H01L25/065 - the devices being of a type provided for in group H01L27/00
H01L25/105 - {the devices being of a type provided for in group H01L27/00}
H01L25/18 - the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L51/00 {
H01L25/50 - {Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
H01L2924/00 - Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L2924/0002 - Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
H01L2924/10253 - Silicon [Si]
H01L2924/1434 - Memory
H01L2924/37001 - Yield

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION

H04L49/101 - {Crossbar or matrix}

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC Y10S - TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

Y10S257/92 - Conductor layers on different levels connected in parallel, e.g. to reduce resistance

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DOE Contract Number:  

B608115

Resource Type:

Patent

Resource Relation:

Patent File Date: 2015 Dec 11

Country of Publication:

United States

Language:

English

Subject:

42 ENGINEERING; 97 MATHEMATICS AND COMPUTING