Global to push GA events into
skip to main content

Title: Program structure-based blocking

Embodiments relate to program structure-based blocking. An aspect includes receiving source code corresponding to a computer program by a compiler of a computer system. Another aspect includes determining a prefetching section in the source code by a marking module of the compiler. Yet another aspect includes performing, by a blocking module of the compiler, blocking of instructions located in the prefetching section into instruction blocks, such that the instruction blocks of the prefetching section only contain instructions that are located in the prefetching section.
Inventors:
; ; ;
Issue Date:
OSTI Identifier:
1399097
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION OSTI
Patent Number(s):
9,772,825
Application Number:
14/741,995
Contract Number:
B599858
Resource Relation:
Patent File Date: 2015 Jun 17
Research Org:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Other works cited in this record:

Method and product involving translation and execution of programs by automatic partitioning and data structure allocation
patent, June 1992

Instruction cache system for implementing programs having non-sequential instructions and method of implementing same
patent, December 1997

Touch history table
patent, April 2000

Method, apparatus and computer programmed product for binary re-optimization using a high level language compiler
patent, September 2001

Method and apparatus for accelerating instruction fetching for a processor
patent, August 2003

Prefetch instruction for an unpredicted path including a flush field for indicating whether earlier prefetches are to be discarded and whether in-progress prefetches are to be aborted
patent, September 2004

Program-directed cache prefetching for media processors
patent, June 2007

Method and apparatus for multicast multiple prefetch
patent, October 2007

Instruction to load data up to a dynamically determined memory boundary
patent, October 2016

Method and system of memory management using stack walking
patent-application, March 2002

Method and apparatus for inserting prefetch instructions in an optimizing compiler
patent-application, May 2003

Program-directed cache prefetching for media processors
patent-application, August 2003

Signal processor, prefetch instruction method and prefetch instruction program
patent-application, September 2004

Zero-overhead loop operation in microprocessor having instruction buffer
patent-application, September 2004

Multiple instruction set architecture code format
patent-application, December 2004

Prefetching Irregular Data References for Software Controlled Caches
patent-application, October 2009

Sequential processor comprising an alu array
patent-application, August 2012

Collision-based alternate hashing
patent-application, December 2013

Next Instruction Access Intent Instruction
patent-application, December 2013

Multi-core processors
patent-application, January 2014

Extract Target Cache Attribute Facility and Instruction Therefore
patent-application, January 2015

Design and evaluation of a compiler algorithm for prefetching
journal, September 1992
  • Mowry, Todd C.; Lam, Monica S.; Gupta, Anoop
  • ACM SIGPLAN Notices, Vol. 27, Issue 9, p. 62-73
  • DOI: 10.1145/143371.143488

An architecture for software-controlled data prefetching
journal, May 1991
  • Klaiber, Alexander C.; Levy, Henry M.
  • ACM SIGARCH Computer Architecture News, Vol. 19, Issue 3, p. 43-53
  • DOI: 10.1145/115953.115958

Data-Driven Multithreading Using Conventional Microprocessors
journal, October 2006
  • Kyriacou, C.; Evripidou, P.; Trancoso, P.
  • IEEE Transactions on Parallel and Distributed Systems, Vol. 17, Issue 10, p. 1176-1188
  • DOI: 10.1109/TPDS.2006.136

A Predictable Execution Model for COTS-Based Embedded Systems
conference, April 2011
  • Pellizzoni, Rodolfo; Betti, Emiliano; Bak, Stanley
  • 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium
  • DOI: 10.1109/RTAS.2011.33

Integrating Caching and Prefetching Mechanisms in a Distributed Transactional Memory
journal, August 2011
  • Dash, Alokika; Demsky, Brian
  • IEEE Transactions on Parallel and Distributed Systems, Vol. 22, Issue 8, p. 1284-1298
  • DOI: 10.1109/TPDS.2011.23

Similar records in DOepatents and OSTI.GOV collections: