Accessing memory
Abstract
A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips. A data access is performed on only the first independently selectable logical sub-rank to access second data via the wide internal data bus. The example method also involves locating a first portion of the first data, a second portion of the first data, and the second data on the narrow external data bus during separate data transfers.
- Inventors:
- Issue Date:
- Research Org.:
- Hewlett Packard Enterprise Development LP, Houston, TX (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1399096
- Patent Number(s):
- 9773531
- Application Number:
- 14/405,904
- Assignee:
- Hewlett Packard Enterprise Development LP
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
- DOE Contract Number:
- SC0005026
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2012 Jun 08
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Yoon, Doe Hyun, Muralimanohar, Naveen, Chang, Jichuan, and Ranganthan, Parthasarathy. Accessing memory. United States: N. p., 2017.
Web.
Yoon, Doe Hyun, Muralimanohar, Naveen, Chang, Jichuan, & Ranganthan, Parthasarathy. Accessing memory. United States.
Yoon, Doe Hyun, Muralimanohar, Naveen, Chang, Jichuan, and Ranganthan, Parthasarathy. Tue .
"Accessing memory". United States. https://www.osti.gov/servlets/purl/1399096.
@article{osti_1399096,
title = {Accessing memory},
author = {Yoon, Doe Hyun and Muralimanohar, Naveen and Chang, Jichuan and Ranganthan, Parthasarathy},
abstractNote = {A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips. A data access is performed on only the first independently selectable logical sub-rank to access second data via the wide internal data bus. The example method also involves locating a first portion of the first data, a second portion of the first data, and the second data on the narrow external data bus during separate data transfers.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2017},
month = {9}
}
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