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Title: Accessing memory

A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips. A data access is performed on only the first independently selectable logical sub-rank to access second data via the wide internal data bus. The example method also involves locating a first portion of the first data, a second portion of the first data, and the second data on the narrow external data bus during separate data transfers.
Inventors:
; ; ;
Issue Date:
OSTI Identifier:
1399096
Assignee:
Hewlett Packard Enterprise Development LP CHO
Patent Number(s):
9,773,531
Application Number:
14/405,904
Contract Number:
SC0005026
Resource Relation:
Patent File Date: 2012 Jun 08
Research Org:
Hewlett Packard Enterprise Development LP, Houston, TX (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Works referenced in this record:

VL-CDRAM: variable line sized cached DRAMs
conference, October 2003
  • Hegde, Ananth; Vijaykrishnan, N.; Kandemir, Mahmut
  • CODES+ISSS '03 Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, p. 132-137
  • DOI: 10.1145/944645.944683